diff options
author | Florian Fainelli <florian@openwrt.org> | 2012-07-04 10:58:35 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2012-07-23 08:54:33 -0400 |
commit | 0f6db0d07289c9ebf46be8909afe2b3772e06015 (patch) | |
tree | f30a0024bac104e223c6dc181ddf7e14a8908aa6 /arch/mips/include/asm/mach-bcm63xx | |
parent | 15514e78381e093dcdbc4613c96e077f0953f049 (diff) |
MIPS: BCM63xx: Define internal registers offsets of the SPI controller
BCM6338, BCM6348, BCM6358 and BCM6368 basically use the same SPI controller
though the internal registers are shuffled, which still allows a common
driver to drive that IP block.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Patchwork: https://patchwork.linux-mips.org/patch/3318/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx')
-rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index e372132086ae..be107e9baf28 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
@@ -973,4 +973,123 @@ | |||
973 | #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) | 973 | #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) |
974 | #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) | 974 | #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) |
975 | 975 | ||
976 | /************************************************************************* | ||
977 | * _REG relative to RSET_SPI | ||
978 | *************************************************************************/ | ||
979 | |||
980 | /* BCM 6338 SPI core */ | ||
981 | #define SPI_6338_CMD 0x00 /* 16-bits register */ | ||
982 | #define SPI_6338_INT_STATUS 0x02 | ||
983 | #define SPI_6338_INT_MASK_ST 0x03 | ||
984 | #define SPI_6338_INT_MASK 0x04 | ||
985 | #define SPI_6338_ST 0x05 | ||
986 | #define SPI_6338_CLK_CFG 0x06 | ||
987 | #define SPI_6338_FILL_BYTE 0x07 | ||
988 | #define SPI_6338_MSG_TAIL 0x09 | ||
989 | #define SPI_6338_RX_TAIL 0x0b | ||
990 | #define SPI_6338_MSG_CTL 0x40 | ||
991 | #define SPI_6338_MSG_DATA 0x41 | ||
992 | #define SPI_6338_MSG_DATA_SIZE 0x3f | ||
993 | #define SPI_6338_RX_DATA 0x80 | ||
994 | #define SPI_6338_RX_DATA_SIZE 0x3f | ||
995 | |||
996 | /* BCM 6348 SPI core */ | ||
997 | #define SPI_6348_CMD 0x00 /* 16-bits register */ | ||
998 | #define SPI_6348_INT_STATUS 0x02 | ||
999 | #define SPI_6348_INT_MASK_ST 0x03 | ||
1000 | #define SPI_6348_INT_MASK 0x04 | ||
1001 | #define SPI_6348_ST 0x05 | ||
1002 | #define SPI_6348_CLK_CFG 0x06 | ||
1003 | #define SPI_6348_FILL_BYTE 0x07 | ||
1004 | #define SPI_6348_MSG_TAIL 0x09 | ||
1005 | #define SPI_6348_RX_TAIL 0x0b | ||
1006 | #define SPI_6348_MSG_CTL 0x40 | ||
1007 | #define SPI_6348_MSG_DATA 0x41 | ||
1008 | #define SPI_6348_MSG_DATA_SIZE 0x3f | ||
1009 | #define SPI_6348_RX_DATA 0x80 | ||
1010 | #define SPI_6348_RX_DATA_SIZE 0x3f | ||
1011 | |||
1012 | /* BCM 6358 SPI core */ | ||
1013 | #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ | ||
1014 | #define SPI_6358_MSG_DATA 0x02 | ||
1015 | #define SPI_6358_MSG_DATA_SIZE 0x21e | ||
1016 | #define SPI_6358_RX_DATA 0x400 | ||
1017 | #define SPI_6358_RX_DATA_SIZE 0x220 | ||
1018 | #define SPI_6358_CMD 0x700 /* 16-bits register */ | ||
1019 | #define SPI_6358_INT_STATUS 0x702 | ||
1020 | #define SPI_6358_INT_MASK_ST 0x703 | ||
1021 | #define SPI_6358_INT_MASK 0x704 | ||
1022 | #define SPI_6358_ST 0x705 | ||
1023 | #define SPI_6358_CLK_CFG 0x706 | ||
1024 | #define SPI_6358_FILL_BYTE 0x707 | ||
1025 | #define SPI_6358_MSG_TAIL 0x709 | ||
1026 | #define SPI_6358_RX_TAIL 0x70B | ||
1027 | |||
1028 | /* BCM 6358 SPI core */ | ||
1029 | #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ | ||
1030 | #define SPI_6368_MSG_DATA 0x02 | ||
1031 | #define SPI_6368_MSG_DATA_SIZE 0x21e | ||
1032 | #define SPI_6368_RX_DATA 0x400 | ||
1033 | #define SPI_6368_RX_DATA_SIZE 0x220 | ||
1034 | #define SPI_6368_CMD 0x700 /* 16-bits register */ | ||
1035 | #define SPI_6368_INT_STATUS 0x702 | ||
1036 | #define SPI_6368_INT_MASK_ST 0x703 | ||
1037 | #define SPI_6368_INT_MASK 0x704 | ||
1038 | #define SPI_6368_ST 0x705 | ||
1039 | #define SPI_6368_CLK_CFG 0x706 | ||
1040 | #define SPI_6368_FILL_BYTE 0x707 | ||
1041 | #define SPI_6368_MSG_TAIL 0x709 | ||
1042 | #define SPI_6368_RX_TAIL 0x70B | ||
1043 | |||
1044 | /* Shared SPI definitions */ | ||
1045 | |||
1046 | /* Message configuration */ | ||
1047 | #define SPI_FD_RW 0x00 | ||
1048 | #define SPI_HD_W 0x01 | ||
1049 | #define SPI_HD_R 0x02 | ||
1050 | #define SPI_BYTE_CNT_SHIFT 0 | ||
1051 | #define SPI_MSG_TYPE_SHIFT 14 | ||
1052 | |||
1053 | /* Command */ | ||
1054 | #define SPI_CMD_NOOP 0x00 | ||
1055 | #define SPI_CMD_SOFT_RESET 0x01 | ||
1056 | #define SPI_CMD_HARD_RESET 0x02 | ||
1057 | #define SPI_CMD_START_IMMEDIATE 0x03 | ||
1058 | #define SPI_CMD_COMMAND_SHIFT 0 | ||
1059 | #define SPI_CMD_COMMAND_MASK 0x000f | ||
1060 | #define SPI_CMD_DEVICE_ID_SHIFT 4 | ||
1061 | #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 | ||
1062 | #define SPI_CMD_ONE_BYTE_SHIFT 11 | ||
1063 | #define SPI_CMD_ONE_WIRE_SHIFT 12 | ||
1064 | #define SPI_DEV_ID_0 0 | ||
1065 | #define SPI_DEV_ID_1 1 | ||
1066 | #define SPI_DEV_ID_2 2 | ||
1067 | #define SPI_DEV_ID_3 3 | ||
1068 | |||
1069 | /* Interrupt mask */ | ||
1070 | #define SPI_INTR_CMD_DONE 0x01 | ||
1071 | #define SPI_INTR_RX_OVERFLOW 0x02 | ||
1072 | #define SPI_INTR_TX_UNDERFLOW 0x04 | ||
1073 | #define SPI_INTR_TX_OVERFLOW 0x08 | ||
1074 | #define SPI_INTR_RX_UNDERFLOW 0x10 | ||
1075 | #define SPI_INTR_CLEAR_ALL 0x1f | ||
1076 | |||
1077 | /* Status */ | ||
1078 | #define SPI_RX_EMPTY 0x02 | ||
1079 | #define SPI_CMD_BUSY 0x04 | ||
1080 | #define SPI_SERIAL_BUSY 0x08 | ||
1081 | |||
1082 | /* Clock configuration */ | ||
1083 | #define SPI_CLK_20MHZ 0x00 | ||
1084 | #define SPI_CLK_0_391MHZ 0x01 | ||
1085 | #define SPI_CLK_0_781MHZ 0x02 /* default */ | ||
1086 | #define SPI_CLK_1_563MHZ 0x03 | ||
1087 | #define SPI_CLK_3_125MHZ 0x04 | ||
1088 | #define SPI_CLK_6_250MHZ 0x05 | ||
1089 | #define SPI_CLK_12_50MHZ 0x06 | ||
1090 | #define SPI_CLK_MASK 0x07 | ||
1091 | #define SPI_SSOFFTIME_MASK 0x38 | ||
1092 | #define SPI_SSOFFTIME_SHIFT 3 | ||
1093 | #define SPI_BYTE_SWAP 0x80 | ||
1094 | |||
976 | #endif /* BCM63XX_REGS_H_ */ | 1095 | #endif /* BCM63XX_REGS_H_ */ |