MIPS: BCM63XX: Add support for bcm6368 CPU.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2892/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 212 insertions, 2 deletions

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 46f03322e2ca..23403a32c158 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
 #define BCM6345_CPU_ID          0x6345
 #define BCM6348_CPU_ID          0x6348
 #define BCM6358_CPU_ID          0x6358
+#define BCM6368_CPU_ID          0x6368
 
 void __init bcm63xx_cpu_init(void);
 u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6358()       (0)
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6368
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()  BCM6368_CPU_ID
+# endif
+# define BCMCPU_IS_6368()       (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
+#else
+# define BCMCPU_IS_6368()       (0)
+#endif
+
 #ifndef bcm63xx_get_cpu_id
 #error "No CPU support configured"
 #endif
@@ -307,6 +321,47 @@ enum bcm63xx_regs_set {
 #define BCM_6358_PCMDMAS_BASE           (0xfffe1a00)
 
 
+/*
+ * 6368 register sets base address
+ */
+#define BCM_6368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6368_PERF_BASE              (0xb0000000)
+#define BCM_6368_TIMER_BASE             (0xb0000040)
+#define BCM_6368_WDT_BASE               (0xb000005c)
+#define BCM_6368_UART0_BASE             (0xb0000100)
+#define BCM_6368_UART1_BASE             (0xb0000120)
+#define BCM_6368_GPIO_BASE              (0xb0000080)
+#define BCM_6368_SPI_BASE               (0xdeadbeef)
+#define BCM_6368_SPI2_BASE              (0xb0000800)
+#define BCM_6368_UDC0_BASE              (0xdeadbeef)
+#define BCM_6368_OHCI0_BASE             (0xb0001600)
+#define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
+#define BCM_6368_MPI_BASE               (0xb0001000)
+#define BCM_6368_PCMCIA_BASE            (0xb0001054)
+#define BCM_6368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6368_M2M_BASE               (0xdeadbeef)
+#define BCM_6368_DSL_BASE               (0xdeadbeef)
+#define BCM_6368_ENET0_BASE             (0xdeadbeef)
+#define BCM_6368_ENET1_BASE             (0xdeadbeef)
+#define BCM_6368_ENETDMA_BASE           (0xb0006800)
+#define BCM_6368_ENETDMAC_BASE          (0xb0006a00)
+#define BCM_6368_ENETDMAS_BASE          (0xb0006c00)
+#define BCM_6368_ENETSW_BASE            (0xb0f00000)
+#define BCM_6368_EHCI0_BASE             (0xb0001500)
+#define BCM_6368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6368_MEMC_BASE              (0xb0001200)
+#define BCM_6368_DDR_BASE               (0xb0001280)
+#define BCM_6368_ATM_BASE               (0xdeadbeef)
+#define BCM_6368_XTM_BASE               (0xb0001800)
+#define BCM_6368_XTMDMA_BASE            (0xb0005000)
+#define BCM_6368_XTMDMAC_BASE           (0xb0005200)
+#define BCM_6368_XTMDMAS_BASE           (0xb0005400)
+#define BCM_6368_PCM_BASE               (0xb0004000)
+#define BCM_6368_PCMDMA_BASE            (0xb0005800)
+#define BCM_6368_PCMDMAC_BASE           (0xb0005a00)
+#define BCM_6368_PCMDMAS_BASE           (0xb0005c00)
+
 
 extern const unsigned long *bcm63xx_regs_base;
 
@@ -410,6 +465,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef CONFIG_BCM63XX_CPU_6358
         __GEN_RSET(6358)
 #endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+        __GEN_RSET(6368)
+#endif
 #endif
         /* unreached */
         return 0;
@@ -574,6 +632,47 @@ enum bcm63xx_irq {
 #define BCM_6358_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
 #define BCM_6358_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
 
+/*
+ * 6368 irqs
+ */
+#define BCM_6368_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_6368_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6368_ENET0_IRQ              0
+#define BCM_6368_ENET1_IRQ              0
+#define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
+#define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
+#define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_PCMCIA_IRQ             0
+#define BCM_6368_ENET0_RXDMA_IRQ        0
+#define BCM_6368_ENET0_TXDMA_IRQ        0
+#define BCM_6368_ENET1_RXDMA_IRQ        0
+#define BCM_6368_ENET1_TXDMA_IRQ        0
+#define BCM_6368_PCI_IRQ                (IRQ_INTERNAL_BASE + 13)
+#define BCM_6368_ATM_IRQ                0
+#define BCM_6368_ENETSW_RXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 0)
+#define BCM_6368_ENETSW_RXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 1)
+#define BCM_6368_ENETSW_RXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 2)
+#define BCM_6368_ENETSW_RXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 3)
+#define BCM_6368_ENETSW_TXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 4)
+#define BCM_6368_ENETSW_TXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 5)
+#define BCM_6368_ENETSW_TXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 6)
+#define BCM_6368_ENETSW_TXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 7)
+#define BCM_6368_XTM_IRQ                (IRQ_INTERNAL_BASE + 11)
+#define BCM_6368_XTM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 8)
+
+#define BCM_6368_PCM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 30)
+#define BCM_6368_PCM_DMA1_IRQ           (BCM_6368_HIGH_IRQ_BASE + 31)
+#define BCM_6368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 20)
+#define BCM_6368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 21)
+#define BCM_6368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 22)
+#define BCM_6368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 23)
+#define BCM_6368_EXT_IRQ4               (IRQ_INTERNAL_BASE + 24)
+#define BCM_6368_EXT_IRQ5               (IRQ_INTERNAL_BASE + 25)
+
 extern const int *bcm63xx_irqs;
 
 #define __GEN_CPU_IRQ_TABLE(__cpu)                                      \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f5..3d5de96d4036 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
                 return 8;
         case BCM6345_CPU_ID:
                 return 16;
+        case BCM6368_CPU_ID:
+                return 38;
         case BCM6348_CPU_ID:
         default:
                 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 2b3a2d6bdb03..50057507c4e7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,6 +83,37 @@
                                         CKCTL_6358_USBSU_EN |           \
                                         CKCTL_6358_EPHY_EN)
 
+#define CKCTL_6368_VDSL_QPROC_EN        (1 << 2)
+#define CKCTL_6368_VDSL_AFE_EN          (1 << 3)
+#define CKCTL_6368_VDSL_BONDING_EN      (1 << 4)
+#define CKCTL_6368_VDSL_EN              (1 << 5)
+#define CKCTL_6368_PHYMIPS_EN           (1 << 6)
+#define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
+#define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
+#define CKCTL_6368_SPI_CLK_EN           (1 << 9)
+#define CKCTL_6368_USBD_CLK_EN          (1 << 10)
+#define CKCTL_6368_SAR_CLK_EN           (1 << 11)
+#define CKCTL_6368_ROBOSW_CLK_EN        (1 << 12)
+#define CKCTL_6368_UTOPIA_CLK_EN        (1 << 13)
+#define CKCTL_6368_PCM_CLK_EN           (1 << 14)
+#define CKCTL_6368_USBH_CLK_EN          (1 << 15)
+#define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
+#define CKCTL_6368_NAND_CLK_EN          (1 << 17)
+#define CKCTL_6368_IPSEC_CLK_EN         (1 << 17)
+
+#define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
+                                        CKCTL_6368_SWPKT_SAR_EN |       \
+                                        CKCTL_6368_SPI_CLK_EN |         \
+                                        CKCTL_6368_USBD_CLK_EN |        \
+                                        CKCTL_6368_SAR_CLK_EN |         \
+                                        CKCTL_6368_ROBOSW_CLK_EN |      \
+                                        CKCTL_6368_UTOPIA_CLK_EN |      \
+                                        CKCTL_6368_PCM_CLK_EN |         \
+                                        CKCTL_6368_USBH_CLK_EN |        \
+                                        CKCTL_6368_DISABLE_GLESS_EN |   \
+                                        CKCTL_6368_NAND_CLK_EN |        \
+                                        CKCTL_6368_IPSEC_CLK_EN)
+
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG            0x8
 #define SYS_PLL_SOFT_RESET              0x1
@@ -92,17 +123,22 @@
 #define PERF_IRQMASK_6345_REG           0xc
 #define PERF_IRQMASK_6348_REG           0xc
 #define PERF_IRQMASK_6358_REG           0xc
+#define PERF_IRQMASK_6368_REG           0x20
 
 /* Interrupt Status register */
 #define PERF_IRQSTAT_6338_REG           0x10
 #define PERF_IRQSTAT_6345_REG           0x10
 #define PERF_IRQSTAT_6348_REG           0x10
 #define PERF_IRQSTAT_6358_REG           0x10
+#define PERF_IRQSTAT_6368_REG           0x28
 
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG_6338        0x14
 #define PERF_EXTIRQ_CFG_REG_6348        0x14
 #define PERF_EXTIRQ_CFG_REG_6358        0x14
+#define PERF_EXTIRQ_CFG_REG_6368        0x18
+
+#define PERF_EXTIRQ_CFG_REG2_6368       0x1c
 
 /* for 6348 only */
 #define EXTIRQ_CFG_SENSE_6348(x)        (1 << (x))
@@ -126,6 +162,7 @@
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG              0x28
+#define PERF_SOFTRESET_6368_REG         0x10
 
 #define SOFTRESET_6338_SPI_MASK         (1 << 0)
 #define SOFTRESET_6338_ENET_MASK        (1 << 2)
@@ -166,6 +203,15 @@
                                   SOFTRESET_6348_ACLC_MASK |            \
                                   SOFTRESET_6348_ADSLMIPSPLL_MASK)
 
+#define SOFTRESET_6368_SPI_MASK         (1 << 0)
+#define SOFTRESET_6368_MPI_MASK         (1 << 3)
+#define SOFTRESET_6368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_6368_SAR_MASK         (1 << 7)
+#define SOFTRESET_6368_ENETSW_MASK      (1 << 10)
+#define SOFTRESET_6368_USBS_MASK        (1 << 11)
+#define SOFTRESET_6368_USBH_MASK        (1 << 12)
+#define SOFTRESET_6368_PCM_MASK         (1 << 13)
+
 /* MIPS PLL control register */
 #define PERF_MIPSPLLCTL_REG             0x34
 #define MIPSPLLCTL_N1_SHIFT             20
@@ -421,6 +467,44 @@
 #define GPIO_MODE_6358_SERIAL_LED       (1 << 10)
 #define GPIO_MODE_6358_UTOPIA           (1 << 12)
 
+#define GPIO_MODE_6368_ANALOG_AFE_0     (1 << 0)
+#define GPIO_MODE_6368_ANALOG_AFE_1     (1 << 1)
+#define GPIO_MODE_6368_SYS_IRQ          (1 << 2)
+#define GPIO_MODE_6368_SERIAL_LED_DATA  (1 << 3)
+#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
+#define GPIO_MODE_6368_INET_LED         (1 << 5)
+#define GPIO_MODE_6368_EPHY0_LED        (1 << 6)
+#define GPIO_MODE_6368_EPHY1_LED        (1 << 7)
+#define GPIO_MODE_6368_EPHY2_LED        (1 << 8)
+#define GPIO_MODE_6368_EPHY3_LED        (1 << 9)
+#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
+#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
+#define GPIO_MODE_6368_ROBOSW_LED0      (1 << 12)
+#define GPIO_MODE_6368_ROBOSW_LED1      (1 << 13)
+#define GPIO_MODE_6368_USBD_LED         (1 << 14)
+#define GPIO_MODE_6368_NTR_PULSE        (1 << 15)
+#define GPIO_MODE_6368_PCI_REQ1         (1 << 16)
+#define GPIO_MODE_6368_PCI_GNT1         (1 << 17)
+#define GPIO_MODE_6368_PCI_INTB         (1 << 18)
+#define GPIO_MODE_6368_PCI_REQ0         (1 << 19)
+#define GPIO_MODE_6368_PCI_GNT0         (1 << 20)
+#define GPIO_MODE_6368_PCMCIA_CD1       (1 << 22)
+#define GPIO_MODE_6368_PCMCIA_CD2       (1 << 23)
+#define GPIO_MODE_6368_PCMCIA_VS1       (1 << 24)
+#define GPIO_MODE_6368_PCMCIA_VS2       (1 << 25)
+#define GPIO_MODE_6368_EBI_CS2          (1 << 26)
+#define GPIO_MODE_6368_EBI_CS3          (1 << 27)
+#define GPIO_MODE_6368_SPI_SSN2         (1 << 28)
+#define GPIO_MODE_6368_SPI_SSN3         (1 << 29)
+#define GPIO_MODE_6368_SPI_SSN4         (1 << 30)
+#define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
+
+
+#define GPIO_BASEMODE_6368_REG          0x38
+#define GPIO_BASEMODE_6368_UART2        0x1
+#define GPIO_BASEMODE_6368_GPIO         0x0
+#define GPIO_BASEMODE_6368_MASK         0x7
+/* those bits must be kept as read in gpio basemode register*/
 
 /*************************************************************************
  * _REG relative to RSET_ENET
@@ -631,7 +715,9 @@
  * _REG relative to RSET_USBH_PRIV
  *************************************************************************/
 
-#define USBH_PRIV_SWAP_REG              0x0
+#define USBH_PRIV_SWAP_6358_REG         0x0
+#define USBH_PRIV_SWAP_6368_REG         0x1c
+
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
@@ -641,7 +727,13 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
-#define USBH_PRIV_TEST_REG              0x24
+#define USBH_PRIV_TEST_6358_REG         0x24
+#define USBH_PRIV_TEST_6368_REG         0x14
+
+#define USBH_PRIV_SETUP_6368_REG        0x28
+#define USBH_PRIV_SETUP_IOC_SHIFT       4
+#define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
+
 
 
 /*************************************************************************
@@ -837,6 +929,19 @@
 #define DMIPSPLLCFG_N2_SHIFT            29
 #define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
 
+#define DDR_DMIPSPLLCFG_6368_REG        0x20
+#define DMIPSPLLCFG_6368_P1_SHIFT       0
+#define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT       4
+#define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT     16
+#define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+
+#define DDR_DMIPSPLLDIV_6368_REG        0x24
+#define DMIPSPLLDIV_6368_MDIV_SHIFT     0
+#define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
+
 /*************************************************************************
  * _REG relative to RSET_M2M
  *************************************************************************/
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index e3fe04dc50bd..ef94ba73646e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,10 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
                 if (offset >= 0xfff00000)
                         return 1;
                 break;
+        case BCM6368_CPU_ID:
+                if (offset >= 0xb0000000 && offset < 0xb1000000)
+                        return 1;
+                break;
         }
         return 0;
 }