MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs

This patch adds initial support for various Atheros SoCs based on the
MIPS 24Kc core. The following models are supported at the moment:

  - AR7130
  - AR7141
  - AR7161
  - AR9130
  - AR9132
  - AR7240
  - AR7241
  - AR7242

The current patch contains minimal support only, but the resulting
kernel can boot into user-space with using of an initramfs image on
various boards which are using these SoCs. Support for more built-in
devices and individual boards will be implemented in further patches.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Cc: Kathy Giori <Kathy.Giori@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1947/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

6 files changed, 452 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
new file mode 100644
index 000000000000..5a9e5e179463
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -0,0 +1,207 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#define AR71XX_APB_BASE         0x18000000
+
+#define AR71XX_DDR_CTRL_BASE    (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE    0x100
+#define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE        0x100
+#define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE         0x100
+#define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE       0x100
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_PCI_WIN0         0x7c
+#define AR71XX_DDR_REG_PCI_WIN1         0x80
+#define AR71XX_DDR_REG_PCI_WIN2         0x84
+#define AR71XX_DDR_REG_PCI_WIN3         0x88
+#define AR71XX_DDR_REG_PCI_WIN4         0x8c
+#define AR71XX_DDR_REG_PCI_WIN5         0x90
+#define AR71XX_DDR_REG_PCI_WIN6         0x94
+#define AR71XX_DDR_REG_PCI_WIN7         0x98
+#define AR71XX_DDR_REG_FLUSH_GE0        0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1        0xa0
+#define AR71XX_DDR_REG_FLUSH_USB        0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI        0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0        0x7c
+#define AR724X_DDR_REG_FLUSH_GE1        0x80
+#define AR724X_DDR_REG_FLUSH_USB        0x84
+#define AR724X_DDR_REG_FLUSH_PCIE       0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0        0x7c
+#define AR913X_DDR_REG_FLUSH_GE1        0x80
+#define AR913X_DDR_REG_FLUSH_USB        0x84
+#define AR913X_DDR_REG_FLUSH_WMAC       0x88
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG       0x00
+#define AR71XX_PLL_REG_SEC_CONFIG       0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK   0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK   0x14
+
+#define AR71XX_PLL_DIV_SHIFT            3
+#define AR71XX_PLL_DIV_MASK             0x1f
+#define AR71XX_CPU_DIV_SHIFT            16
+#define AR71XX_CPU_DIV_MASK             0x3
+#define AR71XX_DDR_DIV_SHIFT            18
+#define AR71XX_DDR_DIV_MASK             0x3
+#define AR71XX_AHB_DIV_SHIFT            20
+#define AR71XX_AHB_DIV_MASK             0x7
+
+#define AR724X_PLL_REG_CPU_CONFIG       0x00
+#define AR724X_PLL_REG_PCIE_CONFIG      0x18
+
+#define AR724X_PLL_DIV_SHIFT            0
+#define AR724X_PLL_DIV_MASK             0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT        10
+#define AR724X_PLL_REF_DIV_MASK         0xf
+#define AR724X_AHB_DIV_SHIFT            19
+#define AR724X_AHB_DIV_MASK             0x1
+#define AR724X_DDR_DIV_SHIFT            22
+#define AR724X_DDR_DIV_MASK             0x3
+
+#define AR913X_PLL_REG_CPU_CONFIG       0x00
+#define AR913X_PLL_REG_ETH_CONFIG       0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK   0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK   0x18
+
+#define AR913X_PLL_DIV_SHIFT            0
+#define AR913X_PLL_DIV_MASK             0x3ff
+#define AR913X_DDR_DIV_SHIFT            22
+#define AR913X_DDR_DIV_MASK             0x3
+#define AR913X_AHB_DIV_SHIFT            19
+#define AR913X_AHB_DIV_MASK             0x1
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER                  0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD           0x04
+#define AR71XX_RESET_REG_WDOG_CTRL              0x08
+#define AR71XX_RESET_REG_WDOG                   0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS        0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE        0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS         0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE         0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS      0x20
+#define AR71XX_RESET_REG_RESET_MODULE           0x24
+#define AR71XX_RESET_REG_PERFC_CTRL             0x2c
+#define AR71XX_RESET_REG_PERFC0                 0x30
+#define AR71XX_RESET_REG_PERFC1                 0x34
+#define AR71XX_RESET_REG_REV_ID                 0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS      0x18
+#define AR913X_RESET_REG_RESET_MODULE           0x1c
+#define AR913X_RESET_REG_PERF_CTRL              0x20
+#define AR913X_RESET_REG_PERFC0                 0x24
+#define AR913X_RESET_REG_PERFC1                 0x28
+
+#define AR724X_RESET_REG_RESET_MODULE           0x1c
+
+#define MISC_INT_DMA                    BIT(7)
+#define MISC_INT_OHCI                   BIT(6)
+#define MISC_INT_PERFC                  BIT(5)
+#define MISC_INT_WDOG                   BIT(4)
+#define MISC_INT_UART                   BIT(3)
+#define MISC_INT_GPIO                   BIT(2)
+#define MISC_INT_ERROR                  BIT(1)
+#define MISC_INT_TIMER                  BIT(0)
+
+#define AR71XX_RESET_EXTERNAL           BIT(28)
+#define AR71XX_RESET_FULL_CHIP          BIT(24)
+#define AR71XX_RESET_CPU_NMI            BIT(21)
+#define AR71XX_RESET_CPU_COLD           BIT(20)
+#define AR71XX_RESET_DMA                BIT(19)
+#define AR71XX_RESET_SLIC               BIT(18)
+#define AR71XX_RESET_STEREO             BIT(17)
+#define AR71XX_RESET_DDR                BIT(16)
+#define AR71XX_RESET_GE1_MAC            BIT(13)
+#define AR71XX_RESET_GE1_PHY            BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE    BIT(10)
+#define AR71XX_RESET_GE0_MAC            BIT(9)
+#define AR71XX_RESET_GE0_PHY            BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL       BIT(6)
+#define AR71XX_RESET_USB_HOST           BIT(5)
+#define AR71XX_RESET_USB_PHY            BIT(4)
+#define AR71XX_RESET_PCI_BUS            BIT(1)
+#define AR71XX_RESET_PCI_CORE           BIT(0)
+
+#define AR724X_RESET_GE1_MDIO           BIT(23)
+#define AR724X_RESET_GE0_MDIO           BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
+#define AR724X_RESET_PCIE_PHY           BIT(7)
+#define AR724X_RESET_PCIE               BIT(6)
+#define AR724X_RESET_OHCI_DLL           BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC          BIT(22)
+
+#define REV_ID_MAJOR_MASK               0xfff0
+#define REV_ID_MAJOR_AR71XX             0x00a0
+#define REV_ID_MAJOR_AR913X             0x00b0
+#define REV_ID_MAJOR_AR7240             0x00c0
+#define REV_ID_MAJOR_AR7241             0x0100
+#define REV_ID_MAJOR_AR7242             0x1100
+
+#define AR71XX_REV_ID_MINOR_MASK        0x3
+#define AR71XX_REV_ID_MINOR_AR7130      0x0
+#define AR71XX_REV_ID_MINOR_AR7141      0x1
+#define AR71XX_REV_ID_MINOR_AR7161      0x2
+#define AR71XX_REV_ID_REVISION_MASK     0x3
+#define AR71XX_REV_ID_REVISION_SHIFT    2
+
+#define AR913X_REV_ID_MINOR_MASK        0x3
+#define AR913X_REV_ID_MINOR_AR9130      0x0
+#define AR913X_REV_ID_MINOR_AR9132      0x1
+#define AR913X_REV_ID_REVISION_MASK     0x3
+#define AR913X_REV_ID_REVISION_SHIFT    2
+
+#define AR724X_REV_ID_REVISION_MASK     0x3
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS       0x00    /* Function Select */
+#define AR71XX_SPI_REG_CTRL     0x04    /* SPI Control */
+#define AR71XX_SPI_REG_IOC      0x08    /* SPI I/O Control */
+#define AR71XX_SPI_REG_RDS      0x0c    /* Read Data Shift */
+
+#define AR71XX_SPI_FS_GPIO      BIT(0)  /* Enable GPIO mode */
+
+#define AR71XX_SPI_CTRL_RD      BIT(6)  /* Remap Disable */
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO       BIT(0)  /* Data Out pin */
+#define AR71XX_SPI_IOC_CLK      BIT(8)  /* CLK pin */
+#define AR71XX_SPI_IOC_CS(n)    BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0      AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1      AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2      AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL   (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
+                                 AR71XX_SPI_IOC_CS2)
+
+#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
new file mode 100644
index 000000000000..6a9f168506fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -0,0 +1,96 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+enum ath79_soc_type {
+        ATH79_SOC_UNKNOWN,
+        ATH79_SOC_AR7130,
+        ATH79_SOC_AR7141,
+        ATH79_SOC_AR7161,
+        ATH79_SOC_AR7240,
+        ATH79_SOC_AR7241,
+        ATH79_SOC_AR7242,
+        ATH79_SOC_AR9130,
+        ATH79_SOC_AR9132
+};
+
+extern enum ath79_soc_type ath79_soc;
+
+static inline int soc_is_ar71xx(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7130 ||
+                ath79_soc == ATH79_SOC_AR7141 ||
+                ath79_soc == ATH79_SOC_AR7161);
+}
+
+static inline int soc_is_ar724x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7240 ||
+                ath79_soc == ATH79_SOC_AR7241 ||
+                ath79_soc == ATH79_SOC_AR7242);
+}
+
+static inline int soc_is_ar7240(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7240);
+}
+
+static inline int soc_is_ar7241(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7241);
+}
+
+static inline int soc_is_ar7242(void)
+{
+        return (ath79_soc == ATH79_SOC_AR7242);
+}
+
+static inline int soc_is_ar913x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9130 ||
+                ath79_soc == ATH79_SOC_AR9132);
+}
+
+extern void __iomem *ath79_ddr_base;
+extern void __iomem *ath79_pll_base;
+extern void __iomem *ath79_reset_base;
+
+static inline void ath79_pll_wr(unsigned reg, u32 val)
+{
+        __raw_writel(val, ath79_pll_base + reg);
+}
+
+static inline u32 ath79_pll_rr(unsigned reg)
+{
+        return __raw_readl(ath79_pll_base + reg);
+}
+
+static inline void ath79_reset_wr(unsigned reg, u32 val)
+{
+        __raw_writel(val, ath79_reset_base + reg);
+}
+
+static inline u32 ath79_reset_rr(unsigned reg)
+{
+        return __raw_readl(ath79_reset_base + reg);
+}
+
+void ath79_device_reset_set(u32 mask);
+void ath79_device_reset_clear(u32 mask);
+
+#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
new file mode 100644
index 000000000000..4476fa03bf36
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X specific CPU feature overrides
+ *
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_sb1_cache       0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr           0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+
+#define cpu_has_prefetch        1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+
+#define cpu_has_mips16          1
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg  0
+#define cpu_has_64bit_gp_regs   0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
new file mode 100644
index 000000000000..189bc6eb9c10
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_ATH79_IRQ_H
+#define __ASM_MACH_ATH79_IRQ_H
+
+#define MIPS_CPU_IRQ_BASE       0
+#define NR_IRQS                 16
+
+#define ATH79_MISC_IRQ_BASE     8
+#define ATH79_MISC_IRQ_COUNT    8
+
+#define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
+#define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
+#define ATH79_CPU_IRQ_GE0       (MIPS_CPU_IRQ_BASE + 4)
+#define ATH79_CPU_IRQ_GE1       (MIPS_CPU_IRQ_BASE + 5)
+#define ATH79_CPU_IRQ_MISC      (MIPS_CPU_IRQ_BASE + 6)
+#define ATH79_CPU_IRQ_TIMER     (MIPS_CPU_IRQ_BASE + 7)
+
+#define ATH79_MISC_IRQ_TIMER    (ATH79_MISC_IRQ_BASE + 0)
+#define ATH79_MISC_IRQ_ERROR    (ATH79_MISC_IRQ_BASE + 1)
+#define ATH79_MISC_IRQ_GPIO     (ATH79_MISC_IRQ_BASE + 2)
+#define ATH79_MISC_IRQ_UART     (ATH79_MISC_IRQ_BASE + 3)
+#define ATH79_MISC_IRQ_WDOG     (ATH79_MISC_IRQ_BASE + 4)
+#define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
+#define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
+#define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
new file mode 100644
index 000000000000..d8d046bccc8e
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
@@ -0,0 +1,32 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X specific kernel entry setup
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H
+#define __ASM_MACH_ATH79_KERNEL_ENTRY_H
+
+        /*
+         * Some bootloaders set the 'Kseg0 coherency algorithm' to
+         * 'Cacheable, noncoherent, write-through, no write allocate'
+         * and this cause performance issues. Let's go and change it to
+         * 'Cacheable, noncoherent, write-back, write allocate'
+         */
+        .macro  kernel_entry_setup
+        mfc0    t0, CP0_CONFIG
+        li      t1, ~CONF_CM_CMASK
+        and     t0, t1
+        ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+        mtc0    t0, CP0_CONFIG
+        nop
+        .endm
+
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
new file mode 100644
index 000000000000..323d9f1d8c45
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_ATH79_WAR_H
+#define __ASM_MACH_ATH79_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MACH_ATH79_WAR_H */