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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/dec
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/dec')
-rw-r--r--arch/mips/include/asm/dec/ecc.h55
-rw-r--r--arch/mips/include/asm/dec/interrupts.h126
-rw-r--r--arch/mips/include/asm/dec/ioasic.h38
-rw-r--r--arch/mips/include/asm/dec/ioasic_addrs.h152
-rw-r--r--arch/mips/include/asm/dec/ioasic_ints.h74
-rw-r--r--arch/mips/include/asm/dec/kn01.h90
-rw-r--r--arch/mips/include/asm/dec/kn02.h91
-rw-r--r--arch/mips/include/asm/dec/kn02ba.h67
-rw-r--r--arch/mips/include/asm/dec/kn02ca.h79
-rw-r--r--arch/mips/include/asm/dec/kn02xa.h84
-rw-r--r--arch/mips/include/asm/dec/kn03.h74
-rw-r--r--arch/mips/include/asm/dec/kn05.h76
-rw-r--r--arch/mips/include/asm/dec/kn230.h26
-rw-r--r--arch/mips/include/asm/dec/machtype.h27
-rw-r--r--arch/mips/include/asm/dec/prom.h174
-rw-r--r--arch/mips/include/asm/dec/system.h19
16 files changed, 1252 insertions, 0 deletions
diff --git a/arch/mips/include/asm/dec/ecc.h b/arch/mips/include/asm/dec/ecc.h
new file mode 100644
index 000000000000..707ffdbc9add
--- /dev/null
+++ b/arch/mips/include/asm/dec/ecc.h
@@ -0,0 +1,55 @@
1/*
2 * include/asm-mips/dec/ecc.h
3 *
4 * ECC handling logic definitions common to DECstation/DECsystem
5 * 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
6 * DECsystem 5900 (KN03), 5900/260 (KN05) systems.
7 *
8 * Copyright (C) 2003 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef __ASM_MIPS_DEC_ECC_H
16#define __ASM_MIPS_DEC_ECC_H
17
18/*
19 * Error Address Register bits.
20 * The register is r/wc -- any write clears it.
21 */
22#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */
23#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */
24#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */
25#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */
26#define KN0X_EAR_RES_27 (1<<27) /* unused */
27#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */
28
29/*
30 * Error Syndrome Register bits.
31 * The register is frozen when EAR.VALID is set, otherwise it records bits
32 * from the last memory read. The register is r/wc -- any write clears it.
33 */
34#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */
35#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */
36#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */
37#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */
38#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */
39#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */
40#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */
41#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */
42
43
44#ifndef __ASSEMBLY__
45
46#include <linux/interrupt.h>
47
48struct pt_regs;
49
50extern void dec_ecc_be_init(void);
51extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
52extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
53#endif
54
55#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/arch/mips/include/asm/dec/interrupts.h b/arch/mips/include/asm/dec/interrupts.h
new file mode 100644
index 000000000000..e10d341067c8
--- /dev/null
+++ b/arch/mips/include/asm/dec/interrupts.h
@@ -0,0 +1,126 @@
1/*
2 * Miscellaneous definitions used to initialise the interrupt vector table
3 * with the machine-specific interrupt routines.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1997 by Paul M. Antoine.
10 * reworked 1998 by Harald Koerfgen.
11 * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki
12 */
13
14#ifndef __ASM_DEC_INTERRUPTS_H
15#define __ASM_DEC_INTERRUPTS_H
16
17#include <irq.h>
18#include <asm/mipsregs.h>
19
20
21/*
22 * The list of possible system devices which provide an
23 * interrupt. Not all devices exist on a given system.
24 */
25#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
26
27/* Ordinary interrupts */
28#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
29#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
30#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */
31#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */
32#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */
33#define DEC_IRQ_FPU 6 /* R3k FPU */
34#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
35#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */
36#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */
37#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */
38#define DEC_IRQ_PSU 11 /* power supply unit warning */
39#define DEC_IRQ_RTC 12 /* DS1287 RTC */
40#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
41#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
42#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */
43#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */
44#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */
45#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */
46#define DEC_IRQ_TIMER 19 /* ARC periodic timer */
47#define DEC_IRQ_VIDEO 20 /* framebuffer */
48
49/* I/O ASIC DMA interrupts */
50#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */
51#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */
52#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */
53#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */
54#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */
55#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */
56#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */
57#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */
58#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */
59#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
60#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */
61#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */
62#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */
63#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */
64#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */
65#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */
66#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */
67#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */
68#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */
69#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */
70
71/* TC5 & TC6 are virtual slots for KN02's onboard devices */
72#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */
73#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */
74
75#define DEC_NR_INTS 41
76
77
78/* Largest of cpu mask_nr tables. */
79#define DEC_MAX_CPU_INTS 6
80/* Largest of asic mask_nr tables. */
81#define DEC_MAX_ASIC_INTS 9
82
83
84/*
85 * CPU interrupt bits common to all systems.
86 */
87#define DEC_CPU_INR_FPU 7 /* R3k FPU */
88#define DEC_CPU_INR_SW1 1 /* software #1 */
89#define DEC_CPU_INR_SW0 0 /* software #0 */
90
91#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */
92
93#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
94#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
95#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
96
97
98#ifndef __ASSEMBLY__
99
100/*
101 * Interrupt table structures to hide differences between systems.
102 */
103typedef union { int i; void *p; } int_ptr;
104extern int dec_interrupt[DEC_NR_INTS];
105extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
106extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
107extern int cpu_fpu_mask;
108
109
110/*
111 * Common interrupt routine prototypes for all DECStations
112 */
113extern void kn02_io_int(void);
114extern void kn02xa_io_int(void);
115extern void kn03_io_int(void);
116extern void asic_dma_int(void);
117extern void asic_all_int(void);
118extern void kn02_all_int(void);
119extern void cpu_all_int(void);
120
121extern void dec_intr_unimplemented(void);
122extern void asic_intr_unimplemented(void);
123
124#endif /* __ASSEMBLY__ */
125
126#endif
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
new file mode 100644
index 000000000000..98badd6bf22d
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-mips/dec/ioasic.h
3 *
4 * DEC I/O ASIC access operations.
5 *
6 * Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#ifndef __ASM_DEC_IOASIC_H
15#define __ASM_DEC_IOASIC_H
16
17#include <linux/spinlock.h>
18#include <linux/types.h>
19
20extern spinlock_t ioasic_ssr_lock;
21
22extern volatile u32 *ioasic_base;
23
24static inline void ioasic_write(unsigned int reg, u32 v)
25{
26 ioasic_base[reg / 4] = v;
27}
28
29static inline u32 ioasic_read(unsigned int reg)
30{
31 return ioasic_base[reg / 4];
32}
33
34extern void init_ioasic_irqs(int base);
35
36extern void dec_ioasic_clocksource_init(void);
37
38#endif /* __ASM_DEC_IOASIC_H */
diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
new file mode 100644
index 000000000000..4cbc1f8a1129
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
@@ -0,0 +1,152 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Definitions for the address map in the JUNKIO Asic
7 *
8 * Created with Information from:
9 *
10 * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
11 *
12 * and the Mach Sources
13 *
14 * Copyright (C) 199x the Anonymous
15 * Copyright (C) 2002, 2003 Maciej W. Rozycki
16 */
17
18#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
19#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
20
21#define IOASIC_SLOT_SIZE 0x00040000
22
23/*
24 * Address ranges decoded by the I/O ASIC for onboard devices.
25 */
26#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */
27#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
28#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
29#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
30#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
31#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
32#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
33#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
34#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */
35#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */
36#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */
37#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */
38#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */
39#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */
40#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
41#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
42#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
43#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
44#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
45
46
47/*
48 * Offsets for I/O ASIC registers
49 * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
50 */
51 /* all systems */
52#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
53#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
54#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */
55#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */
56#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */
57
58 /* except Maxine */
59#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */
60#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */
61
62 /* Maxine */
63#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */
64#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */
65#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */
66#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */
67#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
68#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */
69#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
70
71 /* all systems */
72#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
73#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
74#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
75#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
76
77 /* all systems */
78#define IO_REG_SSR 0x100 /* System Support Register */
79#define IO_REG_SIR 0x110 /* System Interrupt Register */
80#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */
81#define IO_REG_SAR 0x130 /* System Address Register */
82
83 /* Maxine */
84#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */
85#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */
86
87 /* all systems */
88#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */
89#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */
90#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */
91
92 /* except Maxine */
93#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */
94
95 /* Maxine */
96#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */
97#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */
98
99 /* all systems */
100#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
101#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */
102#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */
103#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
104#define IO_REG_RES_31 0x1f0 /* unused */
105
106
107/*
108 * The upper 16 bits of the System Support Register are a part of the
109 * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
110 * machines. The exception is the Maxine, which makes use of the
111 * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
112 * wiring.
113 */
114 /* all systems */
115#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
116#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */
117#define IO_SSR_RES_27 (1<<27) /* unused */
118#define IO_SSR_RES_26 (1<<26) /* unused */
119#define IO_SSR_RES_25 (1<<25) /* unused */
120#define IO_SSR_RES_24 (1<<24) /* unused */
121#define IO_SSR_RES_23 (1<<23) /* unused */
122#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */
123#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */
124#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */
125
126 /* except Maxine */
127#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */
128#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */
129#define IO_SSR_RES_22 (1<<22) /* unused */
130#define IO_SSR_RES_21 (1<<21) /* unused */
131#define IO_SSR_RES_20 (1<<20) /* unused */
132#define IO_SSR_RES_19 (1<<19) /* unused */
133
134 /* Maxine */
135#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */
136#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */
137#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */
138#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */
139#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */
140#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */
141
142/*
143 * The lower 16 bits are system-specific. Bits 15,11:8 are common and
144 * defined here. The rest is defined in system-specific headers.
145 */
146#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */
147#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */
148#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */
149#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */
150#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */
151
152#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
diff --git a/arch/mips/include/asm/dec/ioasic_ints.h b/arch/mips/include/asm/dec/ioasic_ints.h
new file mode 100644
index 000000000000..9aaa9869615f
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic_ints.h
@@ -0,0 +1,74 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Definitions for the interrupt related bits in the I/O ASIC
7 * interrupt status register (and the interrupt mask register, of course)
8 *
9 * Created with Information from:
10 *
11 * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
12 *
13 * and the Mach Sources
14 *
15 * Copyright (C) 199x the Anonymous
16 * Copyright (C) 2002 Maciej W. Rozycki
17 */
18
19#ifndef __ASM_DEC_IOASIC_INTS_H
20#define __ASM_DEC_IOASIC_INTS_H
21
22/*
23 * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
24 * and thus are common to all I/O ASIC machines. The exception is
25 * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
26 * unused) and has a different SCC wiring.
27 */
28 /* all systems */
29#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */
30#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */
31#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */
32#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */
33#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */
34#define IO_INR_ASC_ERR 18 /* ASC page overrun */
35#define IO_INR_ASC_MERR 17 /* ASC memory read error */
36#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */
37
38 /* except Maxine */
39#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */
40#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */
41#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */
42#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */
43#define IO_INR_RES_23 23 /* unused */
44#define IO_INR_RES_22 22 /* unused */
45#define IO_INR_RES_21 21 /* unused */
46#define IO_INR_RES_20 20 /* unused */
47
48 /* Maxine */
49#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */
50#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */
51#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */
52#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */
53#define IO_INR_FLOPPY_ERR 23 /* FDC error */
54#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */
55#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */
56#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */
57
58#define IO_INR_DMA 16 /* first DMA IRQ */
59
60/*
61 * The lower 16 bits are system-specific and thus defined in
62 * system-specific headers.
63 */
64
65
66#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */
67#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */
68
69#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)
70#define IO_IRQ_MASK(n) (1 << (n))
71#define IO_IRQ_ALL 0x0000ffff
72#define IO_IRQ_DMA 0xffff0000
73
74#endif /* __ASM_DEC_IOASIC_INTS_H */
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
new file mode 100644
index 000000000000..28fa717ac423
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -0,0 +1,90 @@
1/*
2 * Hardware info about DECstation DS2100/3100 systems (otherwise known as
3 * pmin/pmax or KN01).
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
10 * are by courtesy of Chris Fraser.
11 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
12 */
13#ifndef __ASM_MIPS_DEC_KN01_H
14#define __ASM_MIPS_DEC_KN01_H
15
16#define KN01_SLOT_BASE 0x10000000
17#define KN01_SLOT_SIZE 0x01000000
18
19/*
20 * Address ranges for devices.
21 */
22#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */
23#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
24#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */
25#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */
26#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */
27#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */
28#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */
29#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */
30#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */
31#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */
32#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */
33#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */
34#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */
35#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */
36#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */
37#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */
38#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
39
40
41/*
42 * Frame buffer memory address.
43 */
44#define KN01_VFB_MEM 0x0fc00000
45
46/*
47 * CPU interrupt bits.
48 */
49#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */
50#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
51#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */
52#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */
53#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
54#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */
55
56
57/*
58 * System Control & Status Register bits.
59 */
60#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
61#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
62#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
63#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
64#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
65#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
66#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
67#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
68#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
69#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */
70#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
71#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
72
73
74#ifndef __ASSEMBLY__
75
76#include <linux/interrupt.h>
77#include <linux/spinlock.h>
78#include <linux/types.h>
79
80struct pt_regs;
81
82extern u16 cached_kn01_csr;
83extern spinlock_t kn01_lock;
84
85extern void dec_kn01_be_init(void);
86extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
87extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id);
88#endif
89
90#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/arch/mips/include/asm/dec/kn02.h b/arch/mips/include/asm/dec/kn02.h
new file mode 100644
index 000000000000..93430b5f4724
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02.h
@@ -0,0 +1,91 @@
1/*
2 * Hardware info about DECstation 5000/200 systems (otherwise known as
3 * 3max or KN02).
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
10 * are by courtesy of Chris Fraser.
11 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
12 */
13#ifndef __ASM_MIPS_DEC_KN02_H
14#define __ASM_MIPS_DEC_KN02_H
15
16#define KN02_SLOT_BASE 0x1fc00000
17#define KN02_SLOT_SIZE 0x00080000
18
19/*
20 * Address ranges decoded by the "system slot" logic for onboard devices.
21 */
22#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */
23#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */
24#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */
25#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */
26#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */
27#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */
28#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */
29#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
30
31
32/*
33 * System Control & Status Register bits.
34 */
35#define KN02_CSR_RES_28 (0xf<<28) /* unused */
36#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
37#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
38#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
39#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
40#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
41#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
42#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
43#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
44#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */
45#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */
46#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
47#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
48#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
49#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
50#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
51
52
53/*
54 * CPU interrupt bits.
55 */
56#define KN02_CPU_INR_RES_6 6 /* unused */
57#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
58#define KN02_CPU_INR_RES_4 4 /* unused */
59#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */
60#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
61
62/*
63 * CSR interrupt bits.
64 */
65#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */
66#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */
67#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */
68#define KN02_CSR_INR_RES_4 4 /* unused */
69#define KN02_CSR_INR_RES_3 3 /* unused */
70#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */
71#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */
72#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */
73
74
75#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
76#define KN02_IRQ_LINES 8 /* number of CSR interrupts */
77
78#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE)
79#define KN02_IRQ_MASK(n) (1 << (n))
80#define KN02_IRQ_ALL 0xff
81
82
83#ifndef __ASSEMBLY__
84
85#include <linux/types.h>
86
87extern u32 cached_kn02_csr;
88extern void init_kn02_irqs(int base);
89#endif
90
91#endif /* __ASM_MIPS_DEC_KN02_H */
diff --git a/arch/mips/include/asm/dec/kn02ba.h b/arch/mips/include/asm/dec/kn02ba.h
new file mode 100644
index 000000000000..c957a4f1b32d
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02ba.h
@@ -0,0 +1,67 @@
1/*
2 * include/asm-mips/dec/kn02ba.h
3 *
4 * DECstation 5000/1xx (3min or KN02-BA) definitions.
5 *
6 * Copyright (C) 2002, 2003 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef __ASM_MIPS_DEC_KN02BA_H
14#define __ASM_MIPS_DEC_KN02BA_H
15
16#include <asm/dec/kn02xa.h> /* For common definitions. */
17
18/*
19 * CPU interrupt bits.
20 */
21#define KN02BA_CPU_INR_HALT 6 /* HALT button */
22#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
23#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */
24#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */
25#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */
26
27/*
28 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
29 */
30#define KN02BA_IO_INR_RES_15 15 /* unused */
31#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
32#define KN02BA_IO_INR_RES_13 13 /* unused */
33#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */
34#define KN02BA_IO_INR_RES_11 11 /* unused */
35#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
36#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
37#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
38#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
39#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
40#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */
41#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */
42#define KN02BA_IO_INR_RES_3 3 /* unused */
43#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
44#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */
45#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */
46
47
48/*
49 * Memory Error Register bits.
50 */
51#define KN02BA_MER_RES_27 (1<<27) /* unused */
52
53/*
54 * Memory Size Register bits.
55 */
56#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */
57
58/*
59 * I/O ASIC System Support Register bits.
60 */
61#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
62#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
63#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */
64
65#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
66
67#endif /* __ASM_MIPS_DEC_KN02BA_H */
diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
new file mode 100644
index 000000000000..92c0fe256099
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -0,0 +1,79 @@
1/*
2 * include/asm-mips/dec/kn02ca.h
3 *
4 * Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
5 *
6 * Copyright (C) 2002, 2003 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef __ASM_MIPS_DEC_KN02CA_H
14#define __ASM_MIPS_DEC_KN02CA_H
15
16#include <asm/dec/kn02xa.h> /* For common definitions. */
17
18/*
19 * CPU interrupt bits.
20 */
21#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */
22#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
23#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */
24#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */
25#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */
26
27/*
28 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
29 */
30#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */
31#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
32#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */
33#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */
34#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */
35#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */
36#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
37#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
38#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
39#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */
40#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
41#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */
42#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */
43#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */
44#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */
45#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */
46#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */
47
48
49/*
50 * Memory Error Register bits.
51 */
52#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */
53
54/*
55 * Memory Size Register bits.
56 */
57#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */
58#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */
59#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */
60#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */
61#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */
62
63/*
64 * I/O ASIC System Support Register bits.
65 */
66#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */
67#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */
68#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
69
70#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
71#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
72#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
73#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
74#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
75#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */
76#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */
77#define KN03CA_IO_SSR_LED (1<<0) /* power LED */
78
79#endif /* __ASM_MIPS_DEC_KN02CA_H */
diff --git a/arch/mips/include/asm/dec/kn02xa.h b/arch/mips/include/asm/dec/kn02xa.h
new file mode 100644
index 000000000000..b56b4577f6ef
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02xa.h
@@ -0,0 +1,84 @@
1/*
2 * Hardware info common to DECstation 5000/1xx systems (otherwise
3 * known as 3min or kn02ba) and Personal DECstations 5000/xx ones
4 * (otherwise known as maxine or kn02ca).
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
11 * are by courtesy of Chris Fraser.
12 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
13 *
14 * These are addresses which have to be known early in the boot process.
15 * For other addresses refer to tc.h, ioasic_addrs.h and friends.
16 */
17#ifndef __ASM_MIPS_DEC_KN02XA_H
18#define __ASM_MIPS_DEC_KN02XA_H
19
20#include <asm/dec/ioasic_addrs.h>
21
22#define KN02XA_SLOT_BASE 0x1c000000
23
24/*
25 * Memory control ASIC registers.
26 */
27#define KN02XA_MER 0x0c400000 /* memory error register */
28#define KN02XA_MSR 0x0c800000 /* memory size register */
29
30/*
31 * CPU control ASIC registers.
32 */
33#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
34#define KN02XA_EAR 0x0e000004 /* error address register */
35#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
36#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
37
38/*
39 * Memory Error Register bits, common definitions.
40 * The rest is defined in system-specific headers.
41 */
42#define KN02XA_MER_RES_28 (0xf<<28) /* unused */
43#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
44#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
45#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
46#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
47#define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */
48#define KN02XA_MER_RES_12 (1<<12) /* unused */
49#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
50#define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */
51#define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */
52#define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */
53#define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */
54#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
55
56/*
57 * Memory Size Register bits, common definitions.
58 * The rest is defined in system-specific headers.
59 */
60#define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */
61#define KN02XA_MSR_RES_14 (0x7<<14) /* unused */
62#define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */
63#define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */
64
65/*
66 * Error Address Register bits.
67 */
68#define KN02XA_EAR_RES_29 (0x7<<29) /* unused */
69#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
70#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
71
72
73#ifndef __ASSEMBLY__
74
75#include <linux/interrupt.h>
76
77struct pt_regs;
78
79extern void dec_kn02xa_be_init(void);
80extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
81extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id);
82#endif
83
84#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/arch/mips/include/asm/dec/kn03.h b/arch/mips/include/asm/dec/kn03.h
new file mode 100644
index 000000000000..edede923ffb8
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn03.h
@@ -0,0 +1,74 @@
1/*
2 * Hardware info about DECstation 5000/2x0 systems (otherwise known as
3 * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
4 * differ mechanically but are otherwise identical (both are known as
5 * KN03).
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
12 * are by courtesy of Chris Fraser.
13 * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
14 */
15#ifndef __ASM_MIPS_DEC_KN03_H
16#define __ASM_MIPS_DEC_KN03_H
17
18#include <asm/dec/ecc.h>
19#include <asm/dec/ioasic_addrs.h>
20
21#define KN03_SLOT_BASE 0x1f800000
22
23/*
24 * CPU interrupt bits.
25 */
26#define KN03_CPU_INR_HALT 6 /* HALT button */
27#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
28#define KN03_CPU_INR_RES_4 4 /* unused */
29#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */
30#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */
31
32/*
33 * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
34 */
35#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */
36#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
37#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */
38#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */
39#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */
40#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
41#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
42#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
43#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
44#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
45#define KN03_IO_INR_RTC 5 /* DS1287 RTC */
46#define KN03_IO_INR_PSU 4 /* power supply unit warning */
47#define KN03_IO_INR_RES_3 3 /* unused */
48#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
49#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */
50#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */
51
52
53/*
54 * Memory Control Register bits.
55 */
56#define KN03_MCR_RES_16 (0xffff<<16) /* unused */
57#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
58#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
59#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */
60#define KN03_MCR_RES_11 (0x3<<12) /* unused */
61#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */
62#define KN03_MCR_RES_7 (0x7<<7) /* unused */
63#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */
64
65/*
66 * I/O ASIC System Support Register bits.
67 */
68#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
69#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
70#define KN03_IO_SSR_RES_12 (1<<12) /* unused */
71
72#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
73
74#endif /* __ASM_MIPS_DEC_KN03_H */
diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h
new file mode 100644
index 000000000000..56d22dc8803a
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn05.h
@@ -0,0 +1,76 @@
1/*
2 * include/asm-mips/dec/kn05.h
3 *
4 * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
5 * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
7 * definitions.
8 *
9 * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 * WARNING! All this information is pure guesswork based on the
17 * ROM. It is provided here in hope it will give someone some
18 * food for thought. No documentation for the KN05 nor the KN04
19 * module has been located so far.
20 */
21#ifndef __ASM_MIPS_DEC_KN05_H
22#define __ASM_MIPS_DEC_KN05_H
23
24#include <asm/dec/ioasic_addrs.h>
25
26/*
27 * The oncard MB (Memory Buffer) ASIC provides an additional address
28 * decoder. Certain address ranges within the "high" 16 slots are
29 * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
30 * Others are handled locally. "Low" slots are always passed.
31 */
32#define KN4K_SLOT_BASE 0x1fc00000
33
34#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
35#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
36#define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
37#define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
38#define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
39#define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
40#define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
41#define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
42#define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
43#define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
44#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
45#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
46#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
47#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
48#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
49#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
50
51/*
52 * Bits for the MB interrupt register.
53 * The register appears read-only.
54 */
55#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
56#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
57#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */
58
59/*
60 * Bits for the MB control & status register.
61 * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
62 */
63#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
64#define KN4K_MB_CSR_F (1<<1) /* ??? */
65#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
66#define KN4K_MB_CSR_OD (1<<10) /* ??? */
67#define KN4K_MB_CSR_CP (1<<11) /* ??? */
68#define KN4K_MB_CSR_UNC (1<<12) /* ??? */
69#define KN4K_MB_CSR_IM (1<<13) /* ??? */
70#define KN4K_MB_CSR_NC (1<<14) /* ??? */
71#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
72#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
73#define KN4K_MB_CSR_FW (1<<21) /* ??? */
74#define KN4K_MB_CSR_W (1<<31) /* ??? */
75
76#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/arch/mips/include/asm/dec/kn230.h b/arch/mips/include/asm/dec/kn230.h
new file mode 100644
index 000000000000..ff1bf17de8d8
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn230.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-mips/dec/kn230.h
3 *
4 * DECsystem 5100 (MIPSmate or KN230) definitions.
5 *
6 * Copyright (C) 2002, 2003 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef __ASM_MIPS_DEC_KN230_H
14#define __ASM_MIPS_DEC_KN230_H
15
16/*
17 * CPU interrupt bits.
18 */
19#define KN230_CPU_INR_HALT 6 /* HALT button */
20#define KN230_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
21#define KN230_CPU_INR_RTC 4 /* DS1287 RTC */
22#define KN230_CPU_INR_SII 3 /* SII (DC7061) SCSI */
23#define KN230_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
24#define KN230_CPU_INR_DZ11 2 /* DZ11 (DC7085) serial */
25
26#endif /* __ASM_MIPS_DEC_KN230_H */
diff --git a/arch/mips/include/asm/dec/machtype.h b/arch/mips/include/asm/dec/machtype.h
new file mode 100644
index 000000000000..a6ecdebc430a
--- /dev/null
+++ b/arch/mips/include/asm/dec/machtype.h
@@ -0,0 +1,27 @@
1/*
2 * Various machine type macros
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 1998, 2000 Harald Koerfgen
9 */
10
11#ifndef __ASM_DEC_MACHTYPE_H
12#define __ASM_DEC_MACHTYPE_H
13
14#include <asm/bootinfo.h>
15
16#define TURBOCHANNEL (mips_machtype == MACH_DS5000_200 || \
17 mips_machtype == MACH_DS5000_1XX || \
18 mips_machtype == MACH_DS5000_XX || \
19 mips_machtype == MACH_DS5000_2X0 || \
20 mips_machtype == MACH_DS5900)
21
22#define IOASIC (mips_machtype == MACH_DS5000_1XX || \
23 mips_machtype == MACH_DS5000_XX || \
24 mips_machtype == MACH_DS5000_2X0 || \
25 mips_machtype == MACH_DS5900)
26
27#endif
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
new file mode 100644
index 000000000000..b9c8203688d5
--- /dev/null
+++ b/arch/mips/include/asm/dec/prom.h
@@ -0,0 +1,174 @@
1/*
2 * include/asm-mips/dec/prom.h
3 *
4 * DECstation PROM interface.
5 *
6 * Copyright (C) 2002 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * Based on arch/mips/dec/prom/prom.h by the Anonymous.
14 */
15#ifndef _ASM_DEC_PROM_H
16#define _ASM_DEC_PROM_H
17
18#include <linux/types.h>
19
20#include <asm/addrspace.h>
21
22/*
23 * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
24 * Many of these will work for MIPSen as well!
25 */
26#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)
27 /* Prom base address */
28
29#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */
30
31#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */
32#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */
33#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6)
34#define PMAX_PROM_READ PMAX_PROM_ENTRY(7)
35#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10)
36#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11)
37#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12)
38#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */
39#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15)
40#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17)
41#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */
42
43
44/*
45 * Magic number indicating REX PROM available on DECstation. Found in
46 * register a2 on transfer of control to program from PROM.
47 */
48#define REX_PROM_MAGIC 0x30464354
49
50#ifdef CONFIG_64BIT
51
52#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
53
54#else /* !CONFIG_64BIT */
55
56#define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC)
57
58#endif /* !CONFIG_64BIT */
59
60
61/*
62 * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
63 * DS5000/2x0.
64 */
65#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */
66#define REX_PROM_GETCHAR 0x24/4 /* getch() */
67#define REX_PROM_GETENV 0x64/4 /* get env. variable */
68#define REX_PROM_GETSYSID 0x80/4 /* get system id */
69#define REX_PROM_GETTCINFO 0xa4/4
70#define REX_PROM_PRINTF 0x30/4 /* printf() */
71#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */
72#define REX_PROM_BOOTINIT 0x54/4 /* open() */
73#define REX_PROM_BOOTREAD 0x58/4 /* read() */
74#define REX_PROM_CLEARCACHE 0x7c/4
75
76
77/*
78 * Used by rex_getbitmap().
79 */
80typedef struct {
81 int pagesize;
82 unsigned char bitmap[0];
83} memmap;
84
85
86/*
87 * Function pointers as read from a PROM's callback vector.
88 */
89extern int (*__rex_bootinit)(void);
90extern int (*__rex_bootread)(void);
91extern int (*__rex_getbitmap)(memmap *);
92extern unsigned long *(*__rex_slot_address)(int);
93extern void *(*__rex_gettcinfo)(void);
94extern int (*__rex_getsysid)(void);
95extern void (*__rex_clear_cache)(void);
96
97extern int (*__prom_getchar)(void);
98extern char *(*__prom_getenv)(char *);
99extern int (*__prom_printf)(char *, ...);
100
101extern int (*__pmax_open)(char*, int);
102extern int (*__pmax_lseek)(int, long, int);
103extern int (*__pmax_read)(int, void *, int);
104extern int (*__pmax_close)(int);
105
106
107#ifdef CONFIG_64BIT
108
109/*
110 * On MIPS64 we have to call PROM functions via a helper
111 * dispatcher to accomodate ABI incompatibilities.
112 */
113#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
114 __asm__(#fun " = call_o32")
115
116int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
117int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
118int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
119unsigned long *__DEC_PROM_O32(_rex_slot_address,
120 (unsigned long *(*)(int), int));
121void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
122int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
123void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
124
125int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
126char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
127int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
128
129
130#define rex_bootinit() _rex_bootinit(__rex_bootinit)
131#define rex_bootread() _rex_bootread(__rex_bootread)
132#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x)
133#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x)
134#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo)
135#define rex_getsysid() _rex_getsysid(__rex_getsysid)
136#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache)
137
138#define prom_getchar() _prom_getchar(__prom_getchar)
139#define prom_getenv(x) _prom_getenv(__prom_getenv, x)
140#define prom_printf(x...) _prom_printf(__prom_printf, x)
141
142#else /* !CONFIG_64BIT */
143
144/*
145 * On plain MIPS we just call PROM functions directly.
146 */
147#define rex_bootinit __rex_bootinit
148#define rex_bootread __rex_bootread
149#define rex_getbitmap __rex_getbitmap
150#define rex_slot_address __rex_slot_address
151#define rex_gettcinfo __rex_gettcinfo
152#define rex_getsysid __rex_getsysid
153#define rex_clear_cache __rex_clear_cache
154
155#define prom_getchar __prom_getchar
156#define prom_getenv __prom_getenv
157#define prom_printf __prom_printf
158
159#define pmax_open __pmax_open
160#define pmax_lseek __pmax_lseek
161#define pmax_read __pmax_read
162#define pmax_close __pmax_close
163
164#endif /* !CONFIG_64BIT */
165
166
167extern void prom_meminit(u32);
168extern void prom_identify_arch(u32);
169extern void prom_init_cmdline(s32, s32 *, u32);
170
171extern void register_prom_console(void);
172extern void unregister_prom_console(void);
173
174#endif /* _ASM_DEC_PROM_H */
diff --git a/arch/mips/include/asm/dec/system.h b/arch/mips/include/asm/dec/system.h
new file mode 100644
index 000000000000..b2afaccd6831
--- /dev/null
+++ b/arch/mips/include/asm/dec/system.h
@@ -0,0 +1,19 @@
1/*
2 * include/asm-mips/dec/system.h
3 *
4 * Generic DECstation/DECsystem bits.
5 *
6 * Copyright (C) 2005, 2006 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13#ifndef __ASM_DEC_SYSTEM_H
14#define __ASM_DEC_SYSTEM_H
15
16extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
17extern int dec_tc_bus;
18
19#endif /* __ASM_DEC_SYSTEM_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 13:30:06 -0500