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authorJoerg Roedel <joerg.roedel@amd.com>2009-06-09 04:50:57 -0400
committerJoerg Roedel <joerg.roedel@amd.com>2009-06-09 04:50:57 -0400
commitd2dd01de9924ae24afeba5aa5bc2e08287701df6 (patch)
tree3021bf496579a48984666355b59df5e44b42dd32 /arch/mips/include/asm/cpu-features.h
parent367d04c4ec02dad34d80452e32e3370db7fb6fee (diff)
parent62a6f465f6572e1f28765c583c12753bb3e23715 (diff)
Merge commit 'tip/core/iommu' into amd-iommu/fixes
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
-rw-r--r--arch/mips/include/asm/cpu-features.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index a0d14f85b781..c0047f861337 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,15 @@
147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
148 cpu_has_mips64r1 | cpu_has_mips64r2) 148 cpu_has_mips64r1 | cpu_has_mips64r2)
149 149
150/*
151 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
152 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
153 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
154 */
155# ifndef cpu_has_clo_clz
156# define cpu_has_clo_clz cpu_has_mips_r
157# endif
158
150#ifndef cpu_has_dsp 159#ifndef cpu_has_dsp
151#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 160#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
152#endif 161#endif