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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 16:44:45 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 16:44:45 -0400
commit8d231c11fd0b694c447e59e687754b6999eea0a2 (patch)
treeb0b3c17efff7018bbf948e489f642c8079f33cc0 /arch/mips/gt64120
parent1f1332f727c3229eb2166a83fec5d3de6a73dce2 (diff)
parent8db089c6b5594c961fb6bc6d613b9926e0d3d98f (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (33 commits) [MIPS] Add missing backslashes to macro definitions. [MIPS] Death list of board support to be removed after 2.6.18. [MIPS] Remove BSD and Sys V compat data types. [MIPS] ioc3.h: Uses u8, so include <linux/types.h>. [MIPS] 74K: Assume it will also have an AR bit in config7 [MIPS] Treat CPUs with AR bit as physically indexed. [MIPS] Oprofile: Support VSMP on 34K. [MIPS] MIPS32/MIPS64 S-cache fix and cleanup [MIPS] excite: PCI makefile needs to use += if it wants a chance to work. [MIPS] excite: plat_setup -> plat_mem_setup. [MIPS] au1xxx: export dbdma functions [MIPS] au1xxx: dbdma, no sleeping under spin_lock [MIPS] au1xxx: fix PSC_SMBTXRX_RSR. [MIPS] Early printk for IP27. [MIPS] Fix handling of 0 length I & D caches. [MIPS] Typo fixes. [MIPS] MIPS32/MIPS64 secondary cache management [MIPS] Fix FIXADDR_TOP for TX39/TX49. [MIPS] Remove first timer interrupt setup in wrppmc_timer_setup() [MIPS] Fix configuration of R2 CPU features and multithreading. ...
Diffstat (limited to 'arch/mips/gt64120')
-rw-r--r--arch/mips/gt64120/common/Makefile1
-rw-r--r--arch/mips/gt64120/common/pci.c147
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c4
-rw-r--r--arch/mips/gt64120/wrppmc/Makefile2
-rw-r--r--arch/mips/gt64120/wrppmc/int-handler.S59
-rw-r--r--arch/mips/gt64120/wrppmc/irq.c20
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c2
-rw-r--r--arch/mips/gt64120/wrppmc/time.c4
8 files changed, 17 insertions, 222 deletions
diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile
index eba5051015a5..1ef676e22ab4 100644
--- a/arch/mips/gt64120/common/Makefile
+++ b/arch/mips/gt64120/common/Makefile
@@ -3,4 +3,3 @@
3# 3#
4 4
5obj-y += time.o 5obj-y += time.o
6obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c
deleted file mode 100644
index e9e5419a0d53..000000000000
--- a/arch/mips/gt64120/common/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Galileo Evaluation Boards PCI support.
4 *
5 * The general-purpose functions to read/write and configure the GT64120A's
6 * PCI registers (function names start with pci0 or pci1) are either direct
7 * copies of functions written by Galileo Technology, or are modifications
8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
9 * are Copyright - Galileo Technology.
10 *
11 * Other functions are derived from other MIPS PCI implementations, or were
12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/init.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/kernel.h>
39#include <asm/gt64120.h>
40
41#define SELF 0
42
43/*
44 * pciXReadConfigReg - Read from a PCI configuration register
45 * - Make sure the GT is configured as a master before
46 * reading from another device on the PCI.
47 * - The function takes care of Big/Little endian conversion.
48 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
49 * spec)
50 * pciDevNum: The device number needs to be addressed.
51 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
52 * cause register to make sure the data is valid
53 *
54 * Configuration Address 0xCF8:
55 *
56 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
57 * |congif|Reserved| Bus |Device|Function|Register|00|
58 * |Enable| |Number|Number| Number | Number | | <=field Name
59 *
60 */
61static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
62{
63 unsigned int DataForRegCf8;
64 unsigned int data;
65
66 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
67 (PCI_FUNC(device->devfn) << 8) |
68 (offset & ~0x3)) | 0x80000000;
69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
70
71 /*
72 * The casual observer might wonder why the READ is duplicated here,
73 * rather than immediately following the WRITE, and just have the swap
74 * in the "if". That's because there is a latency problem with trying
75 * to read immediately after setting up the address register. The "if"
76 * check gives enough time for the address to stabilize, so the READ
77 * can work.
78 */
79 if (PCI_SLOT(device->devfn) == SELF) /* This board */
80 return GT_READ(GT_PCI0_CFGDATA_OFS);
81 else /* PCI is little endian so swap the Data. */
82 return __GT_READ(GT_PCI0_CFGDATA_OFS);
83}
84
85/*
86 * pciXWriteConfigReg - Write to a PCI configuration register
87 * - Make sure the GT is configured as a master before
88 * writingto another device on the PCI.
89 * - The function takes care of Big/Little endian conversion.
90 * Inputs: unsigned int regOffset: The register offset as it apears in the
91 * GT spec
92 * (or any other PCI device spec)
93 * pciDevNum: The device number needs to be addressed.
94 *
95 * Configuration Address 0xCF8:
96 *
97 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
98 * |congif|Reserved| Bus |Device|Function|Register|00|
99 * |Enable| |Number|Number| Number | Number | | <=field Name
100 *
101 */
102static void pci0WriteConfigReg(unsigned int offset,
103 struct pci_dev *device, unsigned int data)
104{
105 unsigned int DataForRegCf8;
106
107 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
108 (PCI_FUNC(device->devfn) << 8) |
109 (offset & ~0x3)) | 0x80000000;
110 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
111
112 if (PCI_SLOT(device->devfn) == SELF) /* This board */
113 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
114 else /* configuration Transaction over the pci. */
115 __GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
116}
117
118extern struct pci_ops gt64120_pci_ops;
119
120void __init pcibios_init(void)
121{
122 u32 tmp;
123 struct pci_dev controller;
124
125 controller.devfn = SELF;
126
127 tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
128 tmp = GT_READ(GT_PCI0_BARE_OFS);
129
130 /*
131 * You have to enable bus mastering to configure any other
132 * card on the bus.
133 */
134 tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
135 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
136 pci0WriteConfigReg(PCI_COMMAND, &controller, tmp);
137
138 /*
139 * Reset PCI I/O and PCI MEM values to ones supported by EVM.
140 */
141 ioport_resource.start = GT_PCI_IO_BASE;
142 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
143 iomem_resource.start = GT_PCI_MEM_BASE;
144 iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1;
145
146 pci_scan_bus(0, &gt64120_pci_ops, NULL);
147}
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 1193a22c4693..9804642ecf89 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -164,8 +164,8 @@ void __init plat_mem_setup(void)
164 pm_power_off = momenco_ocelot_power_off; 164 pm_power_off = momenco_ocelot_power_off;
165 165
166 /* 166 /*
167 * initrd_start = (ulong)ocelot_initrd_start; 167 * initrd_start = (unsigned long)ocelot_initrd_start;
168 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; 168 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
169 * initrd_below_start_ok = 1; 169 * initrd_below_start_ok = 1;
170 */ 170 */
171 171
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile
index 72606b9af12a..7cf52205511c 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/gt64120/wrppmc/Makefile
@@ -9,6 +9,6 @@
9# Makefile for the Wind River MIPS 4KC PPMC Eval Board 9# Makefile for the Wind River MIPS 4KC PPMC Eval Board
10# 10#
11 11
12obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o 12obj-y += irq.o reset.o setup.o time.o pci.o
13 13
14EXTRA_AFLAGS := $(CFLAGS) 14EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S
deleted file mode 100644
index edee7b394175..000000000000
--- a/arch/mips/gt64120/wrppmc/int-handler.S
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
7 * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
8 */
9#include <asm/asm.h>
10#include <asm/mipsregs.h>
11#include <asm/addrspace.h>
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/mach-wrppmc/mach-gt64120.h>
15
16 .align 5
17 .set noat
18NESTED(handle_IRQ, PT_SIZE, sp)
19 SAVE_ALL
20 CLI # Important: mark KERNEL mode !
21 .set at
22
23 mfc0 t0, CP0_CAUSE # get pending interrupts
24 mfc0 t1, CP0_STATUS # get enabled interrupts
25 and t0, t0, t1 # get allowed interrupts
26 andi t0, t0, 0xFF00
27 beqz t0, 1f
28 move a1, sp # Prepare 'struct pt_regs *regs' pointer
29
30 andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer
31 bnez t1, handle_cputimer_irq
32 andi t1, t0, CAUSEF_IP6 # UART 16550 port
33 bnez t1, handle_uart_irq
34 andi t1, t0, CAUSEF_IP3 # PCI INT_A
35 bnez t1, handle_pci_intA_irq
36
37 /* wrong alarm or masked ... */
381: j spurious_interrupt
39 nop
40END(handle_IRQ)
41
42 .align 5
43handle_cputimer_irq:
44 li a0, WRPPMC_MIPS_TIMER_IRQ
45 jal do_IRQ
46 j ret_from_irq
47
48 .align 5
49handle_uart_irq:
50 li a0, WRPPMC_UART16550_IRQ
51 jal do_IRQ
52 j ret_from_irq
53
54 .align 5
55handle_pci_intA_irq:
56 li a0, WRPPMC_PCI_INTA_IRQ
57 jal do_IRQ
58 j ret_from_irq
59
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index 8605687e24ed..8d75a43ce877 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -30,7 +30,19 @@
30#include <asm/irq_cpu.h> 30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h> 31#include <asm/gt64120.h>
32 32
33extern asmlinkage void handle_IRQ(void); 33asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
34{
35 unsigned int pending = read_c0_status() & read_c0_cause();
36
37 if (pending & STATUSF_IP7)
38 do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */
39 else if (pending & STATUSF_IP6)
40 do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */
41 else if (pending & STATUSF_IP3)
42 do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */
43 else
44 spurious_interrupt(regs);
45}
34 46
35/** 47/**
36 * Initialize GT64120 Interrupt Controller 48 * Initialize GT64120 Interrupt Controller
@@ -50,12 +62,6 @@ void gt64120_init_pic(void)
50 62
51void __init arch_init_irq(void) 63void __init arch_init_irq(void)
52{ 64{
53 /* enable all CPU interrupt bits. */
54 set_c0_status(ST0_IM); /* IE bit is still 0 */
55
56 /* Install MIPS Interrupt Trap Vector */
57 set_except_vector(0, handle_IRQ);
58
59 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ 65 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
60 mips_cpu_irq_init(0); 66 mips_cpu_irq_init(0);
61 67
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index 20c591e49dae..2db6375ef29e 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -125,7 +125,7 @@ static void wrppmc_setup_serial(void)
125} 125}
126#endif 126#endif
127 127
128void __init plat_setup(void) 128void __init plat_mem_setup(void)
129{ 129{
130 extern void wrppmc_time_init(void); 130 extern void wrppmc_time_init(void);
131 extern void wrppmc_timer_setup(struct irqaction *); 131 extern void wrppmc_timer_setup(struct irqaction *);
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c
index 175d22adb450..6c24a82df0dd 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/gt64120/wrppmc/time.c
@@ -31,10 +31,6 @@ void __init wrppmc_timer_setup(struct irqaction *irq)
31{ 31{
32 /* Install ISR for timer interrupt */ 32 /* Install ISR for timer interrupt */
33 setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); 33 setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq);
34
35 /* to generate the first timer interrupt */
36 write_c0_compare(mips_hpt_frequency/HZ);
37 write_c0_count(0);
38} 34}
39 35
40/* 36/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 18:20:50 -0400