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authorMark.Zhan <rongkai.zhan@windriver.com>2006-06-20 06:15:02 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-29 16:10:34 -0400
commit9247857f5acadf0ea87fd6a9514c633644634f08 (patch)
tree77ce13d9b8ef0076622a0225ac6b8b1607a80260 /arch/mips/gt64120
parent0a6047eef1c465c38aacfbdab193161b3f0cd144 (diff)
[MIPS] Fix the build error of Wind River PPMC board, rewrite irq code to C
o Fix the build error Wind River PPMC board caused by the change of plat_setup hook interface. o Rewrite first level interrupt dispatch code to C. Signed-off-by: Rongkai.Zhan <rongkai.zhan@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/gt64120')
-rw-r--r--arch/mips/gt64120/wrppmc/Makefile2
-rw-r--r--arch/mips/gt64120/wrppmc/int-handler.S59
-rw-r--r--arch/mips/gt64120/wrppmc/irq.c17
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c2
4 files changed, 15 insertions, 65 deletions
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile
index 72606b9af12a..7cf52205511c 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/gt64120/wrppmc/Makefile
@@ -9,6 +9,6 @@
9# Makefile for the Wind River MIPS 4KC PPMC Eval Board 9# Makefile for the Wind River MIPS 4KC PPMC Eval Board
10# 10#
11 11
12obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o 12obj-y += irq.o reset.o setup.o time.o pci.o
13 13
14EXTRA_AFLAGS := $(CFLAGS) 14EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S
deleted file mode 100644
index edee7b394175..000000000000
--- a/arch/mips/gt64120/wrppmc/int-handler.S
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
7 * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
8 */
9#include <asm/asm.h>
10#include <asm/mipsregs.h>
11#include <asm/addrspace.h>
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/mach-wrppmc/mach-gt64120.h>
15
16 .align 5
17 .set noat
18NESTED(handle_IRQ, PT_SIZE, sp)
19 SAVE_ALL
20 CLI # Important: mark KERNEL mode !
21 .set at
22
23 mfc0 t0, CP0_CAUSE # get pending interrupts
24 mfc0 t1, CP0_STATUS # get enabled interrupts
25 and t0, t0, t1 # get allowed interrupts
26 andi t0, t0, 0xFF00
27 beqz t0, 1f
28 move a1, sp # Prepare 'struct pt_regs *regs' pointer
29
30 andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer
31 bnez t1, handle_cputimer_irq
32 andi t1, t0, CAUSEF_IP6 # UART 16550 port
33 bnez t1, handle_uart_irq
34 andi t1, t0, CAUSEF_IP3 # PCI INT_A
35 bnez t1, handle_pci_intA_irq
36
37 /* wrong alarm or masked ... */
381: j spurious_interrupt
39 nop
40END(handle_IRQ)
41
42 .align 5
43handle_cputimer_irq:
44 li a0, WRPPMC_MIPS_TIMER_IRQ
45 jal do_IRQ
46 j ret_from_irq
47
48 .align 5
49handle_uart_irq:
50 li a0, WRPPMC_UART16550_IRQ
51 jal do_IRQ
52 j ret_from_irq
53
54 .align 5
55handle_pci_intA_irq:
56 li a0, WRPPMC_PCI_INTA_IRQ
57 jal do_IRQ
58 j ret_from_irq
59
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index 8605687e24ed..26cf360f1694 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -30,7 +30,19 @@
30#include <asm/irq_cpu.h> 30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h> 31#include <asm/gt64120.h>
32 32
33extern asmlinkage void handle_IRQ(void); 33asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
34{
35 unsigned int pending = read_c0_status() & read_c0_cause();
36
37 if (pending & STATUSF_IP7)
38 do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */
39 else if (pending & STATUSF_IP6)
40 do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */
41 else if (pending & STATUSF_IP3)
42 do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */
43 else
44 spurious_interrupt(regs);
45}
34 46
35/** 47/**
36 * Initialize GT64120 Interrupt Controller 48 * Initialize GT64120 Interrupt Controller
@@ -53,9 +65,6 @@ void __init arch_init_irq(void)
53 /* enable all CPU interrupt bits. */ 65 /* enable all CPU interrupt bits. */
54 set_c0_status(ST0_IM); /* IE bit is still 0 */ 66 set_c0_status(ST0_IM); /* IE bit is still 0 */
55 67
56 /* Install MIPS Interrupt Trap Vector */
57 set_except_vector(0, handle_IRQ);
58
59 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ 68 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
60 mips_cpu_irq_init(0); 69 mips_cpu_irq_init(0);
61 70
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index 20c591e49dae..2db6375ef29e 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -125,7 +125,7 @@ static void wrppmc_setup_serial(void)
125} 125}
126#endif 126#endif
127 127
128void __init plat_setup(void) 128void __init plat_mem_setup(void)
129{ 129{
130 extern void wrppmc_time_init(void); 130 extern void wrppmc_time_init(void);
131 extern void wrppmc_timer_setup(struct irqaction *); 131 extern void wrppmc_timer_setup(struct irqaction *);