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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-06-21 02:06:21 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:33:00 -0400
commit6b5bf509317c013ea0a7c166affc1d4631720d85 (patch)
tree09c4cfaea1feca577930edbb7e382b573c98290e /arch/mips/gt64120
parent36de48de85bdb9bc8c35c1eb513737c187d70a46 (diff)
[MIPS] EV64120: Remove support
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/gt64120')
-rw-r--r--arch/mips/gt64120/ev64120/Kconfig3
-rw-r--r--arch/mips/gt64120/ev64120/Makefile9
-rw-r--r--arch/mips/gt64120/ev64120/irq.c116
-rw-r--r--arch/mips/gt64120/ev64120/promcon.c48
-rw-r--r--arch/mips/gt64120/ev64120/reset.c45
-rw-r--r--arch/mips/gt64120/ev64120/serialGT.c212
-rw-r--r--arch/mips/gt64120/ev64120/setup.c99
7 files changed, 0 insertions, 532 deletions
diff --git a/arch/mips/gt64120/ev64120/Kconfig b/arch/mips/gt64120/ev64120/Kconfig
deleted file mode 100644
index d691762cb0f7..000000000000
--- a/arch/mips/gt64120/ev64120/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
1config EVB_PCI1
2 bool "Enable Second PCI (PCI1)"
3 depends on MIPS_EV64120
diff --git a/arch/mips/gt64120/ev64120/Makefile b/arch/mips/gt64120/ev64120/Makefile
deleted file mode 100644
index 323b2cebc691..000000000000
--- a/arch/mips/gt64120/ev64120/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Copyright 2000 RidgeRun, Inc.
3# Author: RidgeRun, Inc.
4# glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5#
6# Makefile for the Galileo EV64120 board.
7#
8
9obj-y += irq.o promcon.o reset.o serialGT.o setup.o
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
deleted file mode 100644
index 64e4c80b6139..000000000000
--- a/arch/mips/gt64120/ev64120/irq.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Code to handle irqs on GT64120A boards
4 * Derived from mips/orion and Cort <cort@fsmlabs.com>
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: RidgeRun, Inc.
8 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/kernel_stat.h>
33#include <linux/module.h>
34#include <linux/signal.h>
35#include <linux/sched.h>
36#include <linux/types.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/timex.h>
40#include <linux/slab.h>
41#include <linux/random.h>
42#include <linux/bitops.h>
43#include <asm/bootinfo.h>
44#include <asm/io.h>
45#include <asm/mipsregs.h>
46#include <asm/system.h>
47#include <asm/gt64120.h>
48
49asmlinkage void plat_irq_dispatch(void)
50{
51 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
52
53 if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
54 do_IRQ(4);
55 else if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(GT_INTA);
57 else if (pending & STATUSF_IP5) /* int3 hardware line */
58 do_IRQ(GT_INTD);
59 else if (pending & STATUSF_IP6) /* int4 hardware line */
60 do_IRQ(6);
61 else if (pending & STATUSF_IP7) /* compare int */
62 do_IRQ(7);
63 else
64 spurious_interrupt();
65}
66
67static void disable_ev64120_irq(unsigned int irq_nr)
68{
69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
70 clear_c0_status(9 << 10);
71 } else {
72 clear_c0_status(1 << (irq_nr + 8));
73 }
74}
75
76static void enable_ev64120_irq(unsigned int irq_nr)
77{
78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
79 set_c0_status(9 << 10);
80 else
81 set_c0_status(1 << (irq_nr + 8));
82}
83
84static void end_ev64120_irq(unsigned int irq)
85{
86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
87 enable_ev64120_irq(irq);
88}
89
90static struct irq_chip ev64120_irq_type = {
91 .name = "EV64120",
92 .ack = disable_ev64120_irq,
93 .mask = disable_ev64120_irq,
94 .mask_ack = disable_ev64120_irq,
95 .unmask = enable_ev64120_irq,
96 .end = end_ev64120_irq,
97};
98
99void gt64120_irq_setup(void)
100{
101 /*
102 * Clear all of the interrupts while we change the able around a bit.
103 */
104 clear_c0_status(ST0_IM);
105
106 /*
107 * Enable timer. Other interrupts will be enabled as they are
108 * registered.
109 */
110 set_c0_status(IE_IRQ2);
111}
112
113void __init arch_init_irq(void)
114{
115 gt64120_irq_setup();
116}
diff --git a/arch/mips/gt64120/ev64120/promcon.c b/arch/mips/gt64120/ev64120/promcon.c
deleted file mode 100644
index 6e0ecfed9640..000000000000
--- a/arch/mips/gt64120/ev64120/promcon.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * Wrap-around code for a console using the
3 * SGI PROM io-routines.
4 *
5 * Copyright (c) 1999 Ulf Carlsson
6 *
7 * Derived from DECstation promcon.c
8 * Copyright (c) 1998 Harald Koerfgen
9 */
10#include <linux/tty.h>
11#include <linux/init.h>
12#include <linux/console.h>
13
14static void prom_console_write(struct console *co, const char *s,
15 unsigned count)
16{
17 extern int CONSOLE_CHANNEL; // The default serial port
18 unsigned i;
19
20 for (i = 0; i < count; i++) {
21 if (*s == 10)
22 serial_putc(CONSOLE_CHANNEL, 13);
23 serial_putc(CONSOLE_CHANNEL, *s++);
24 }
25}
26
27static struct console sercons = {
28 .name = "ttyS",
29 .write = prom_console_write,
30 .flags = CON_PRINTBUFFER,
31 .index = -1,
32};
33
34/*
35 * Register console.
36 */
37
38static int gal_serial_console_init(void)
39{
40 // serial_init();
41 //serial_set(115200);
42
43 register_console(&sercons);
44
45 return 0;
46}
47
48console_initcall(gal_serial_console_init);
diff --git a/arch/mips/gt64120/ev64120/reset.c b/arch/mips/gt64120/ev64120/reset.c
deleted file mode 100644
index 7b9f5e5bf21f..000000000000
--- a/arch/mips/gt64120/ev64120/reset.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997 Ralf Baechle
7 */
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <asm/io.h>
11#include <asm/pgtable.h>
12#include <asm/processor.h>
13#include <asm/reboot.h>
14#include <asm/system.h>
15
16void galileo_machine_restart(char *command)
17{
18 *(volatile char *) 0xbc000000 = 0x0f;
19 /*
20 * Ouch, we're still alive ... This time we take the silver bullet ...
21 * ... and find that we leave the hardware in a state in which the
22 * kernel in the flush locks up somewhen during of after the PCI
23 * detection stuff.
24 */
25 set_c0_status(ST0_BEV | ST0_ERL);
26 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
27 flush_cache_all();
28 write_c0_wired(0);
29 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
30}
31
32void galileo_machine_halt(void)
33{
34 printk(KERN_NOTICE "You can safely turn off the power\n");
35 while (1)
36 __asm__(".set\tmips3\n\t"
37 "wait\n\t"
38 ".set\tmips0");
39
40}
41
42void galileo_machine_power_off(void)
43{
44 galileo_machine_halt();
45}
diff --git a/arch/mips/gt64120/ev64120/serialGT.c b/arch/mips/gt64120/ev64120/serialGT.c
deleted file mode 100644
index 8f0d835491ff..000000000000
--- a/arch/mips/gt64120/ev64120/serialGT.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 * serialGT.c
3 *
4 * BRIEF MODULE DESCRIPTION
5 * Low Level Serial Port control for use
6 * with the Galileo EVB64120A MIPS eval board and
7 * its on board two channel 16552 Uart.
8 *
9 * Copyright (C) 2000 RidgeRun, Inc.
10 * Author: RidgeRun, Inc.
11 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 */
34
35// Note:
36// Serial CHANNELS - 0 is the bottom connector of evb64120A.
37// (The one that maps to the "B" channel of the
38// board's uart)
39// 1 is the top connector of evb64120A.
40// (The one that maps to the "A" channel of the
41// board's uart)
42int DEBUG_CHANNEL = 0; // See Note Above
43int CONSOLE_CHANNEL = 1; // See Note Above
44
45#define DUART 0xBD000000 /* Base address of Uart. */
46#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA
47 register set of the 16552 Uart device.
48 DUART+0 gets you to the ChanB register set.
49 */
50#define DUART_DELTA 0x4
51#define FIFO_ENABLE 0x07
52#define INT_ENABLE 0x04 /* default interrupt mask */
53
54#define RBR 0x00
55#define THR 0x00
56#define DLL 0x00
57#define IER 0x01
58#define DLM 0x01
59#define IIR 0x02
60#define FCR 0x02
61#define LCR 0x03
62#define MCR 0x04
63#define LSR 0x05
64#define MSR 0x06
65#define SCR 0x07
66
67#define LCR_DLAB 0x80
68#define XTAL 1843200
69#define LSR_THRE 0x20
70#define LSR_BI 0x10
71#define LSR_DR 0x01
72#define MCR_LOOP 0x10
73#define ACCESS_DELAY 0x10000
74
75/******************************
76 Routine:
77 Description:
78 ******************************/
79int inreg(int channel, int reg)
80{
81 int val;
82 val =
83 *((volatile unsigned char *) DUART +
84 (channel * CHANNELOFFSET) + (reg * DUART_DELTA));
85 return val;
86}
87
88/******************************
89 Routine:
90 Description:
91 ******************************/
92void outreg(int channel, int reg, unsigned char val)
93{
94 *((volatile unsigned char *) DUART + (channel * CHANNELOFFSET)
95 + (reg * DUART_DELTA)) = val;
96}
97
98/******************************
99 Routine:
100 Description:
101 Initialize the device driver.
102 ******************************/
103void serial_init(int channel)
104{
105 /*
106 * Configure active port, (CHANNELOFFSET already set.)
107 *
108 * Set 8 bits, 1 stop bit, no parity.
109 *
110 * LCR<7> 0 divisor latch access bit
111 * LCR<6> 0 break control (1=send break)
112 * LCR<5> 0 stick parity (0=space, 1=mark)
113 * LCR<4> 0 parity even (0=odd, 1=even)
114 * LCR<3> 0 parity enable (1=enabled)
115 * LCR<2> 0 # stop bits (0=1, 1=1.5)
116 * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
117 */
118 outreg(channel, LCR, 0x3);
119
120 outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */
121
122 outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */
123}
124
125/******************************
126 Routine:
127 Description:
128 Set the baud rate.
129 ******************************/
130void serial_set(int channel, unsigned long baud)
131{
132 unsigned char sav_lcr;
133
134 /*
135 * Enable access to the divisor latches by setting DLAB in LCR.
136 *
137 */
138 sav_lcr = inreg(channel, LCR);
139
140#if 0
141 /*
142 * Set baud rate
143 */
144 outreg(channel, LCR, LCR_DLAB | sav_lcr);
145 // outreg(DLL,(XTAL/(16*2*(baud))-2));
146 outreg(channel, DLL, XTAL / (16 * baud));
147 // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
148 outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
149#else
150 /*
151 * Note: Set baud rate, hardcoded here for rate of 115200
152 * since became unsure of above "baud rate" algorithm (??).
153 */
154 outreg(channel, LCR, 0x83);
155 outreg(channel, DLM, 0x00); // See note above
156 outreg(channel, DLL, 0x02); // See note above.
157 outreg(channel, LCR, 0x03);
158#endif
159
160 /*
161 * Restore line control register
162 */
163 outreg(channel, LCR, sav_lcr);
164}
165
166
167/******************************
168 Routine:
169 Description:
170 Transmit a character.
171 ******************************/
172void serial_putc(int channel, int c)
173{
174 while ((inreg(channel, LSR) & LSR_THRE) == 0);
175 outreg(channel, THR, c);
176}
177
178/******************************
179 Routine:
180 Description:
181 Read a received character if one is
182 available. Return -1 otherwise.
183 ******************************/
184int serial_getc(int channel)
185{
186 if (inreg(channel, LSR) & LSR_DR) {
187 return inreg(channel, RBR);
188 }
189 return -1;
190}
191
192/******************************
193 Routine:
194 Description:
195 Used by embedded gdb client. (example; gdb-stub.c)
196 ******************************/
197char getDebugChar()
198{
199 int val;
200 while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in.
201 return (char) val;
202}
203
204/******************************
205 Routine:
206 Description:
207 Used by embedded gdb target. (example; gdb-stub.c)
208 ******************************/
209void putDebugChar(char c)
210{
211 serial_putc(DEBUG_CHANNEL, (int) c);
212}
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
deleted file mode 100644
index 477848c22a2c..000000000000
--- a/arch/mips/gt64120/ev64120/setup.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/types.h>
30#include <linux/mm.h>
31#include <linux/swap.h>
32#include <linux/ioport.h>
33#include <linux/sched.h>
34#include <linux/interrupt.h>
35#include <linux/pci.h>
36#include <linux/timex.h>
37#include <linux/pm.h>
38
39#include <asm/bootinfo.h>
40#include <asm/page.h>
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/pci.h>
44#include <asm/processor.h>
45#include <asm/time.h>
46#include <asm/reboot.h>
47#include <asm/traps.h>
48#include <linux/bootmem.h>
49
50unsigned long gt64120_base = KSEG1ADDR(0x14000000);
51
52/* These functions are used for rebooting or halting the machine*/
53extern void galileo_machine_restart(char *command);
54extern void galileo_machine_halt(void);
55extern void galileo_machine_power_off(void);
56/*
57 *This structure holds pointers to the pci configuration space accesses
58 *and interrupts allocating routine for device over the PCI
59 */
60extern struct pci_ops galileo_pci_ops;
61
62void __init prom_free_prom_memory(void)
63{
64}
65
66/*
67 * Initializes basic routines and structures pointers, memory size (as
68 * given by the bios and saves the command line.
69 */
70
71void __init plat_mem_setup(void)
72{
73 _machine_restart = galileo_machine_restart;
74 _machine_halt = galileo_machine_halt;
75 pm_power_off = galileo_machine_power_off;
76
77 set_io_port_base(KSEG1);
78}
79
80const char *get_system_type(void)
81{
82 return "Galileo EV64120A";
83}
84
85/*
86 * Kernel arguments passed by the firmware
87 *
88 * $a0 - nothing
89 * $a1 - holds a pointer to the eprom parameters
90 * $a2 - nothing
91 */
92
93void __init prom_init(void)
94{
95 mips_machgroup = MACH_GROUP_GALILEO;
96 mips_machtype = MACH_EV64120A;
97
98 add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
99}
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