diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/gt64120/common |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'arch/mips/gt64120/common')
-rw-r--r-- | arch/mips/gt64120/common/Makefile | 6 | ||||
-rw-r--r-- | arch/mips/gt64120/common/pci.c | 147 | ||||
-rw-r--r-- | arch/mips/gt64120/common/time.c | 100 |
3 files changed, 253 insertions, 0 deletions
diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile new file mode 100644 index 000000000000..eba5051015a5 --- /dev/null +++ b/arch/mips/gt64120/common/Makefile | |||
@@ -0,0 +1,6 @@ | |||
1 | # | ||
2 | # Makefile for common code of gt64120-based boards. | ||
3 | # | ||
4 | |||
5 | obj-y += time.o | ||
6 | obj-$(CONFIG_PCI) += pci.o | ||
diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c new file mode 100644 index 000000000000..e9e5419a0d53 --- /dev/null +++ b/arch/mips/gt64120/common/pci.c | |||
@@ -0,0 +1,147 @@ | |||
1 | /* | ||
2 | * BRIEF MODULE DESCRIPTION | ||
3 | * Galileo Evaluation Boards PCI support. | ||
4 | * | ||
5 | * The general-purpose functions to read/write and configure the GT64120A's | ||
6 | * PCI registers (function names start with pci0 or pci1) are either direct | ||
7 | * copies of functions written by Galileo Technology, or are modifications | ||
8 | * of their functions to work with Linux 2.4 vs Linux 2.2. These functions | ||
9 | * are Copyright - Galileo Technology. | ||
10 | * | ||
11 | * Other functions are derived from other MIPS PCI implementations, or were | ||
12 | * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. | ||
13 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify it | ||
16 | * under the terms of the GNU General Public License as published by the | ||
17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
18 | * option) any later version. | ||
19 | * | ||
20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
30 | * | ||
31 | * You should have received a copy of the GNU General Public License along | ||
32 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
34 | */ | ||
35 | #include <linux/init.h> | ||
36 | #include <linux/types.h> | ||
37 | #include <linux/pci.h> | ||
38 | #include <linux/kernel.h> | ||
39 | #include <asm/gt64120.h> | ||
40 | |||
41 | #define SELF 0 | ||
42 | |||
43 | /* | ||
44 | * pciXReadConfigReg - Read from a PCI configuration register | ||
45 | * - Make sure the GT is configured as a master before | ||
46 | * reading from another device on the PCI. | ||
47 | * - The function takes care of Big/Little endian conversion. | ||
48 | * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI | ||
49 | * spec) | ||
50 | * pciDevNum: The device number needs to be addressed. | ||
51 | * RETURNS: data , if the data == 0xffffffff check the master abort bit in the | ||
52 | * cause register to make sure the data is valid | ||
53 | * | ||
54 | * Configuration Address 0xCF8: | ||
55 | * | ||
56 | * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number | ||
57 | * |congif|Reserved| Bus |Device|Function|Register|00| | ||
58 | * |Enable| |Number|Number| Number | Number | | <=field Name | ||
59 | * | ||
60 | */ | ||
61 | static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) | ||
62 | { | ||
63 | unsigned int DataForRegCf8; | ||
64 | unsigned int data; | ||
65 | |||
66 | DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | | ||
67 | (PCI_FUNC(device->devfn) << 8) | | ||
68 | (offset & ~0x3)) | 0x80000000; | ||
69 | GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); | ||
70 | |||
71 | /* | ||
72 | * The casual observer might wonder why the READ is duplicated here, | ||
73 | * rather than immediately following the WRITE, and just have the swap | ||
74 | * in the "if". That's because there is a latency problem with trying | ||
75 | * to read immediately after setting up the address register. The "if" | ||
76 | * check gives enough time for the address to stabilize, so the READ | ||
77 | * can work. | ||
78 | */ | ||
79 | if (PCI_SLOT(device->devfn) == SELF) /* This board */ | ||
80 | return GT_READ(GT_PCI0_CFGDATA_OFS); | ||
81 | else /* PCI is little endian so swap the Data. */ | ||
82 | return __GT_READ(GT_PCI0_CFGDATA_OFS); | ||
83 | } | ||
84 | |||
85 | /* | ||
86 | * pciXWriteConfigReg - Write to a PCI configuration register | ||
87 | * - Make sure the GT is configured as a master before | ||
88 | * writingto another device on the PCI. | ||
89 | * - The function takes care of Big/Little endian conversion. | ||
90 | * Inputs: unsigned int regOffset: The register offset as it apears in the | ||
91 | * GT spec | ||
92 | * (or any other PCI device spec) | ||
93 | * pciDevNum: The device number needs to be addressed. | ||
94 | * | ||
95 | * Configuration Address 0xCF8: | ||
96 | * | ||
97 | * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number | ||
98 | * |congif|Reserved| Bus |Device|Function|Register|00| | ||
99 | * |Enable| |Number|Number| Number | Number | | <=field Name | ||
100 | * | ||
101 | */ | ||
102 | static void pci0WriteConfigReg(unsigned int offset, | ||
103 | struct pci_dev *device, unsigned int data) | ||
104 | { | ||
105 | unsigned int DataForRegCf8; | ||
106 | |||
107 | DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | | ||
108 | (PCI_FUNC(device->devfn) << 8) | | ||
109 | (offset & ~0x3)) | 0x80000000; | ||
110 | GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); | ||
111 | |||
112 | if (PCI_SLOT(device->devfn) == SELF) /* This board */ | ||
113 | GT_WRITE(GT_PCI0_CFGDATA_OFS, data); | ||
114 | else /* configuration Transaction over the pci. */ | ||
115 | __GT_WRITE(GT_PCI0_CFGDATA_OFS, data); | ||
116 | } | ||
117 | |||
118 | extern struct pci_ops gt64120_pci_ops; | ||
119 | |||
120 | void __init pcibios_init(void) | ||
121 | { | ||
122 | u32 tmp; | ||
123 | struct pci_dev controller; | ||
124 | |||
125 | controller.devfn = SELF; | ||
126 | |||
127 | tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ | ||
128 | tmp = GT_READ(GT_PCI0_BARE_OFS); | ||
129 | |||
130 | /* | ||
131 | * You have to enable bus mastering to configure any other | ||
132 | * card on the bus. | ||
133 | */ | ||
134 | tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); | ||
135 | tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | ||
136 | pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); | ||
137 | |||
138 | /* | ||
139 | * Reset PCI I/O and PCI MEM values to ones supported by EVM. | ||
140 | */ | ||
141 | ioport_resource.start = GT_PCI_IO_BASE; | ||
142 | ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; | ||
143 | iomem_resource.start = GT_PCI_MEM_BASE; | ||
144 | iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1; | ||
145 | |||
146 | pci_scan_bus(0, >64120_pci_ops, NULL); | ||
147 | } | ||
diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c new file mode 100644 index 000000000000..2287b59536e5 --- /dev/null +++ b/arch/mips/gt64120/common/time.c | |||
@@ -0,0 +1,100 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or modify it | ||
3 | * under the terms of the GNU General Public License as published by the | ||
4 | * Free Software Foundation; either version 2 of the License, or (at your | ||
5 | * option) any later version. | ||
6 | * | ||
7 | * Galileo Technology chip interrupt handler | ||
8 | */ | ||
9 | #include <linux/interrupt.h> | ||
10 | #include <linux/kernel.h> | ||
11 | #include <linux/config.h> | ||
12 | #include <linux/sched.h> | ||
13 | #include <linux/kernel_stat.h> | ||
14 | #include <asm/ptrace.h> | ||
15 | #include <asm/gt64120.h> | ||
16 | |||
17 | /* | ||
18 | * These are interrupt handlers for the GT on-chip interrupts. They all come | ||
19 | * in to the MIPS on a single interrupt line, and have to be handled and ack'ed | ||
20 | * differently than other MIPS interrupts. | ||
21 | */ | ||
22 | |||
23 | static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs) | ||
24 | { | ||
25 | unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; | ||
26 | int handled = 0; | ||
27 | |||
28 | irq_src = GT_READ(GT_INTRCAUSE_OFS); | ||
29 | irq_src_mask = GT_READ(GT_INTRMASK_OFS); | ||
30 | int_high_src = GT_READ(GT_HINTRCAUSE_OFS); | ||
31 | int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); | ||
32 | irq_src = irq_src & irq_src_mask; | ||
33 | int_high_src = int_high_src & int_high_src_mask; | ||
34 | |||
35 | if (irq_src & 0x00000800) { /* Check for timer interrupt */ | ||
36 | handled = 1; | ||
37 | irq_src &= ~0x00000800; | ||
38 | do_timer(regs); | ||
39 | #ifndef CONFIG_SMP | ||
40 | update_process_times(user_mode(regs)); | ||
41 | #endif | ||
42 | } | ||
43 | |||
44 | GT_WRITE(GT_INTRCAUSE_OFS, 0); | ||
45 | GT_WRITE(GT_HINTRCAUSE_OFS, 0); | ||
46 | } | ||
47 | |||
48 | /* | ||
49 | * Initializes timer using galileo's built in timer. | ||
50 | */ | ||
51 | #ifdef CONFIG_SYSCLK_100 | ||
52 | #define Sys_clock (100 * 1000000) // 100 MHz | ||
53 | #endif | ||
54 | #ifdef CONFIG_SYSCLK_83 | ||
55 | #define Sys_clock (83.333 * 1000000) // 83.333 MHz | ||
56 | #endif | ||
57 | #ifdef CONFIG_SYSCLK_75 | ||
58 | #define Sys_clock (75 * 1000000) // 75 MHz | ||
59 | #endif | ||
60 | |||
61 | /* | ||
62 | * This will ignore the standard MIPS timer interrupt handler that is passed in | ||
63 | * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt | ||
64 | * handling. | ||
65 | */ | ||
66 | void gt64120_time_init(void) | ||
67 | { | ||
68 | static struct irqaction timer; | ||
69 | |||
70 | /* Disable timer first */ | ||
71 | GT_WRITE(GT_TC_CONTROL_OFS, 0); | ||
72 | /* Load timer value for 100 Hz */ | ||
73 | GT_WRITE(GT_TC3_OFS, Sys_clock / 100); | ||
74 | |||
75 | /* | ||
76 | * Create the IRQ structure entry for the timer. Since we're too early | ||
77 | * in the boot process to use the "request_irq()" call, we'll hard-code | ||
78 | * the values to the correct interrupt line. | ||
79 | */ | ||
80 | timer.handler = gt64120_irq; | ||
81 | timer.flags = SA_SHIRQ | SA_INTERRUPT; | ||
82 | timer.name = "timer"; | ||
83 | timer.dev_id = NULL; | ||
84 | timer.next = NULL; | ||
85 | timer.mask = CPU_MASK_NONE; | ||
86 | irq_desc[GT_TIMER].action = &timer; | ||
87 | |||
88 | enable_irq(GT_TIMER); | ||
89 | |||
90 | /* Enable timer ints */ | ||
91 | GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); | ||
92 | /* clear Cause register first */ | ||
93 | GT_WRITE(GT_INTRCAUSE_OFS, 0x0); | ||
94 | /* Unmask timer int */ | ||
95 | GT_WRITE(GT_INTRMASK_OFS, 0x800); | ||
96 | /* Clear High int register */ | ||
97 | GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); | ||
98 | /* Mask All interrupts at High cause interrupt */ | ||
99 | GT_WRITE(GT_HINTRMASK_OFS, 0x0); | ||
100 | } | ||