MIPS: EMMA2RH: Remove useless CPU_IRQ_BASE

For historical reasons, we used to put MIPS CPU IRQs behind SoC-specific
IRQs in the queue, and have been using CPU_IRQ_BASE as MIPS_CPU_IRQ_BASE.
In recent years, however, we've brought it back to normal order, and now
CPU_IRQ_BASE just redefines the generic MIPS_CPU_IRQ_BASE.

At the same time, NUM_CPU_IRQ is also removed as useless.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1387/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9504b7ee0b7c..1d1c806056c5 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
         /* setup cascade interrupts */
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-        setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+        setup_irq(MIPS_CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP7)
-                do_IRQ(CPU_IRQ_BASE + 7);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & STATUSF_IP2)
                 emma2rh_irq_dispatch();
         else if (pending & STATUSF_IP1)
-                do_IRQ(CPU_IRQ_BASE + 1);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 1);
         else if (pending & STATUSF_IP0)
-                do_IRQ(CPU_IRQ_BASE + 0);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 0);
         else
                 spurious_interrupt();
 }