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authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-10-23 12:32:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-27 12:18:30 -0400
commit9ae9fd79af28d6488e97311a3b60379b59ff4c90 (patch)
tree3146a83f9d1245d0ab0448326cd97dd5db25589c /arch/mips/emma
parentfcb3cfe7f087fb27c35be911791883fb725055b1 (diff)
MIPS: EMMA: Fold arch/mips/emma/{common,markeins}/irq*.c into markeins/irq.c
Current EMMA2RH irq code is mess. Before cleaning it up, gather them in one place as a first step. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/emma')
-rw-r--r--arch/mips/emma/common/Makefile2
-rw-r--r--arch/mips/emma/common/irq.c105
-rw-r--r--arch/mips/emma/common/irq_emma2rh.c103
-rw-r--r--arch/mips/emma/markeins/Makefile2
-rw-r--r--arch/mips/emma/markeins/irq.c251
-rw-r--r--arch/mips/emma/markeins/irq_markeins.c153
6 files changed, 249 insertions, 367 deletions
diff --git a/arch/mips/emma/common/Makefile b/arch/mips/emma/common/Makefile
index cb0fd328c61f..c392d28c1ef1 100644
--- a/arch/mips/emma/common/Makefile
+++ b/arch/mips/emma/common/Makefile
@@ -10,4 +10,4 @@
10# (at your option) any later version. 10# (at your option) any later version.
11# 11#
12 12
13obj-$(CONFIG_NEC_MARKEINS) += irq.o irq_emma2rh.o prom.o 13obj-$(CONFIG_NEC_MARKEINS) += prom.o
diff --git a/arch/mips/emma/common/irq.c b/arch/mips/emma/common/irq.c
deleted file mode 100644
index 4158f808aa8e..000000000000
--- a/arch/mips/emma/common/irq.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * arch/mips/emma2rh/common/irq.c
3 * This file is common irq dispatcher.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/types.h>
29
30#include <asm/system.h>
31#include <asm/mipsregs.h>
32#include <asm/addrspace.h>
33#include <asm/bootinfo.h>
34
35#include <asm/emma/emma2rh.h>
36
37/*
38 * the first level int-handler will jump here if it is a emma2rh irq
39 */
40void emma2rh_irq_dispatch(void)
41{
42 u32 intStatus;
43 u32 bitmask;
44 u32 i;
45
46 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
47 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
48
49#ifdef EMMA2RH_SW_CASCADE
50 if (intStatus &
51 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
52 u32 swIntStatus;
53 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
54 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
55 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
56 if (swIntStatus & bitmask) {
57 do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
58 return;
59 }
60 }
61 }
62#endif
63
64 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
65 if (intStatus & bitmask) {
66 do_IRQ(EMMA2RH_IRQ_BASE + i);
67 return;
68 }
69 }
70
71 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
72 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
73
74#ifdef EMMA2RH_GPIO_CASCADE
75 if (intStatus &
76 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
77 u32 gpioIntStatus;
78 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
79 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
80 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
81 if (gpioIntStatus & bitmask) {
82 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
83 return;
84 }
85 }
86 }
87#endif
88
89 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
90 if (intStatus & bitmask) {
91 do_IRQ(EMMA2RH_IRQ_BASE + i);
92 return;
93 }
94 }
95
96 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
97 & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
98
99 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
100 if (intStatus & bitmask) {
101 do_IRQ(EMMA2RH_IRQ_BASE + i);
102 return;
103 }
104 }
105}
diff --git a/arch/mips/emma/common/irq_emma2rh.c b/arch/mips/emma/common/irq_emma2rh.c
deleted file mode 100644
index 4f84fede4c4c..000000000000
--- a/arch/mips/emma/common/irq_emma2rh.c
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * arch/mips/emma2rh/common/irq_emma2rh.c
3 * This file defines the irq handler for EMMA2RH.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26/*
27 * EMMA2RH defines 64 IRQs.
28 *
29 * This file exports one function:
30 * emma2rh_irq_init(u32 irq_base);
31 */
32
33#include <linux/interrupt.h>
34#include <linux/types.h>
35#include <linux/ptrace.h>
36
37#include <asm/debug.h>
38
39#include <asm/emma/emma2rh.h>
40
41/* number of total irqs supported by EMMA2RH */
42#define NUM_EMMA2RH_IRQ 96
43
44void ll_emma2rh_irq_enable(int);
45void ll_emma2rh_irq_disable(int);
46
47static void emma2rh_irq_enable(unsigned int irq)
48{
49 ll_emma2rh_irq_enable(irq - EMMA2RH_IRQ_BASE);
50}
51
52static void emma2rh_irq_disable(unsigned int irq)
53{
54 ll_emma2rh_irq_disable(irq - EMMA2RH_IRQ_BASE);
55}
56
57struct irq_chip emma2rh_irq_controller = {
58 .name = "emma2rh_irq",
59 .ack = emma2rh_irq_disable,
60 .mask = emma2rh_irq_disable,
61 .mask_ack = emma2rh_irq_disable,
62 .unmask = emma2rh_irq_enable,
63};
64
65void emma2rh_irq_init(void)
66{
67 u32 i;
68
69 for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
70 set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
71 &emma2rh_irq_controller,
72 handle_level_irq);
73}
74
75void ll_emma2rh_irq_enable(int emma2rh_irq)
76{
77 u32 reg_value;
78 u32 reg_bitmask;
79 u32 reg_index;
80
81 reg_index = EMMA2RH_BHIF_INT_EN_0
82 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
83 * (emma2rh_irq / 32);
84 reg_value = emma2rh_in32(reg_index);
85 reg_bitmask = 0x1 << (emma2rh_irq % 32);
86 db_assert((reg_value & reg_bitmask) == 0);
87 emma2rh_out32(reg_index, reg_value | reg_bitmask);
88}
89
90void ll_emma2rh_irq_disable(int emma2rh_irq)
91{
92 u32 reg_value;
93 u32 reg_bitmask;
94 u32 reg_index;
95
96 reg_index = EMMA2RH_BHIF_INT_EN_0
97 + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
98 * (emma2rh_irq / 32);
99 reg_value = emma2rh_in32(reg_index);
100 reg_bitmask = 0x1 << (emma2rh_irq % 32);
101 db_assert((reg_value & reg_bitmask) != 0);
102 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
103}
diff --git a/arch/mips/emma/markeins/Makefile b/arch/mips/emma/markeins/Makefile
index 3c8b864f7bc5..16e0017ba919 100644
--- a/arch/mips/emma/markeins/Makefile
+++ b/arch/mips/emma/markeins/Makefile
@@ -10,4 +10,4 @@
10# (at your option) any later version. 10# (at your option) any later version.
11# 11#
12 12
13obj-$(CONFIG_NEC_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o 13obj-$(CONFIG_NEC_MARKEINS) += irq.o setup.o led.o platform.o
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 3577fd52030d..ada33d8f6edf 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -38,6 +38,9 @@
38 38
39#include <asm/emma/emma2rh.h> 39#include <asm/emma/emma2rh.h>
40 40
41/* number of total irqs supported by EMMA2RH */
42#define NUM_EMMA2RH_IRQ 96
43
41/* 44/*
42 * IRQ mapping 45 * IRQ mapping
43 * 46 *
@@ -53,10 +56,180 @@
53 * 56 *
54 */ 57 */
55 58
56extern void emma2rh_sw_irq_init(void); 59void ll_emma2rh_irq_enable(int emma2rh_irq)
57extern void emma2rh_gpio_irq_init(void); 60{
58extern void emma2rh_irq_init(void); 61 u32 reg_value;
59extern void emma2rh_irq_dispatch(void); 62 u32 reg_bitmask;
63 u32 reg_index;
64
65 reg_index = EMMA2RH_BHIF_INT_EN_0 +
66 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) *
67 (emma2rh_irq / 32);
68 reg_value = emma2rh_in32(reg_index);
69 reg_bitmask = 0x1 << (emma2rh_irq % 32);
70 db_assert((reg_value & reg_bitmask) == 0);
71 emma2rh_out32(reg_index, reg_value | reg_bitmask);
72}
73
74void ll_emma2rh_irq_disable(int emma2rh_irq)
75{
76 u32 reg_value;
77 u32 reg_bitmask;
78 u32 reg_index;
79
80 reg_index = EMMA2RH_BHIF_INT_EN_0 +
81 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) *
82 (emma2rh_irq / 32);
83 reg_value = emma2rh_in32(reg_index);
84 reg_bitmask = 0x1 << (emma2rh_irq % 32);
85 db_assert((reg_value & reg_bitmask) != 0);
86 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
87}
88
89static void emma2rh_irq_enable(unsigned int irq)
90{
91 ll_emma2rh_irq_enable(irq - EMMA2RH_IRQ_BASE);
92}
93
94static void emma2rh_irq_disable(unsigned int irq)
95{
96 ll_emma2rh_irq_disable(irq - EMMA2RH_IRQ_BASE);
97}
98
99struct irq_chip emma2rh_irq_controller = {
100 .name = "emma2rh_irq",
101 .ack = emma2rh_irq_disable,
102 .mask = emma2rh_irq_disable,
103 .mask_ack = emma2rh_irq_disable,
104 .unmask = emma2rh_irq_enable,
105};
106
107void emma2rh_irq_init(void)
108{
109 u32 i;
110
111 for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
112 set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
113 &emma2rh_irq_controller,
114 handle_level_irq);
115}
116
117void ll_emma2rh_sw_irq_enable(int irq)
118{
119 u32 reg;
120
121 db_assert(irq >= 0);
122 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
123
124 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
125 reg |= 1 << irq;
126 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
127}
128
129void ll_emma2rh_sw_irq_disable(int irq)
130{
131 u32 reg;
132
133 db_assert(irq >= 0);
134 db_assert(irq < 32);
135
136 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
137 reg &= ~(1 << irq);
138 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
139}
140
141static void emma2rh_sw_irq_enable(unsigned int irq)
142{
143 ll_emma2rh_sw_irq_enable(irq - EMMA2RH_SW_IRQ_BASE);
144}
145
146static void emma2rh_sw_irq_disable(unsigned int irq)
147{
148 ll_emma2rh_sw_irq_disable(irq - EMMA2RH_SW_IRQ_BASE);
149}
150
151struct irq_chip emma2rh_sw_irq_controller = {
152 .name = "emma2rh_sw_irq",
153 .ack = emma2rh_sw_irq_disable,
154 .mask = emma2rh_sw_irq_disable,
155 .mask_ack = emma2rh_sw_irq_disable,
156 .unmask = emma2rh_sw_irq_enable,
157};
158
159void emma2rh_sw_irq_init(void)
160{
161 u32 i;
162
163 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
164 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
165 &emma2rh_sw_irq_controller,
166 handle_level_irq);
167}
168
169void ll_emma2rh_gpio_irq_enable(int irq)
170{
171 u32 reg;
172
173 db_assert(irq >= 0);
174 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
175
176 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
177 reg |= 1 << irq;
178 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
179}
180
181void ll_emma2rh_gpio_irq_disable(int irq)
182{
183 u32 reg;
184
185 db_assert(irq >= 0);
186 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
187
188 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
189 reg &= ~(1 << irq);
190 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
191}
192
193static void emma2rh_gpio_irq_enable(unsigned int irq)
194{
195 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
196}
197
198static void emma2rh_gpio_irq_disable(unsigned int irq)
199{
200 ll_emma2rh_gpio_irq_disable(irq - EMMA2RH_GPIO_IRQ_BASE);
201}
202
203static void emma2rh_gpio_irq_ack(unsigned int irq)
204{
205 irq -= EMMA2RH_GPIO_IRQ_BASE;
206 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
207 ll_emma2rh_gpio_irq_disable(irq);
208}
209
210static void emma2rh_gpio_irq_end(unsigned int irq)
211{
212 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
213 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
214}
215
216struct irq_chip emma2rh_gpio_irq_controller = {
217 .name = "emma2rh_gpio_irq",
218 .ack = emma2rh_gpio_irq_ack,
219 .mask = emma2rh_gpio_irq_disable,
220 .mask_ack = emma2rh_gpio_irq_ack,
221 .unmask = emma2rh_gpio_irq_enable,
222 .end = emma2rh_gpio_irq_end,
223};
224
225void emma2rh_gpio_irq_init(void)
226{
227 u32 i;
228
229 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
230 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
231 &emma2rh_gpio_irq_controller);
232}
60 233
61static struct irqaction irq_cascade = { 234static struct irqaction irq_cascade = {
62 .handler = no_action, 235 .handler = no_action,
@@ -67,6 +240,76 @@ static struct irqaction irq_cascade = {
67 .next = NULL, 240 .next = NULL,
68}; 241};
69 242
243/*
244 * the first level int-handler will jump here if it is a emma2rh irq
245 */
246void emma2rh_irq_dispatch(void)
247{
248 u32 intStatus;
249 u32 bitmask;
250 u32 i;
251
252 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) &
253 emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
254
255#ifdef EMMA2RH_SW_CASCADE
256 if (intStatus &
257 (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
258 u32 swIntStatus;
259 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
260 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
261 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
262 if (swIntStatus & bitmask) {
263 do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
264 return;
265 }
266 }
267 }
268#endif
269
270 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
271 if (intStatus & bitmask) {
272 do_IRQ(EMMA2RH_IRQ_BASE + i);
273 return;
274 }
275 }
276
277 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) &
278 emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
279
280#ifdef EMMA2RH_GPIO_CASCADE
281 if (intStatus &
282 (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
283 u32 gpioIntStatus;
284 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
285 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
286 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
287 if (gpioIntStatus & bitmask) {
288 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
289 return;
290 }
291 }
292 }
293#endif
294
295 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
296 if (intStatus & bitmask) {
297 do_IRQ(EMMA2RH_IRQ_BASE + i);
298 return;
299 }
300 }
301
302 intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) &
303 emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
304
305 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
306 if (intStatus & bitmask) {
307 do_IRQ(EMMA2RH_IRQ_BASE + i);
308 return;
309 }
310 }
311}
312
70void __init arch_init_irq(void) 313void __init arch_init_irq(void)
71{ 314{
72 u32 reg; 315 u32 reg;
diff --git a/arch/mips/emma/markeins/irq_markeins.c b/arch/mips/emma/markeins/irq_markeins.c
deleted file mode 100644
index ea27ec573d95..000000000000
--- a/arch/mips/emma/markeins/irq_markeins.c
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * arch/mips/emma2rh/markeins/irq_markeins.c
3 * This file defines the irq handler for Mark-eins.
4 *
5 * Copyright (C) NEC Electronics Corporation 2004-2006
6 *
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/types.h>
28#include <linux/ptrace.h>
29
30#include <asm/debug.h>
31#include <asm/emma/emma2rh.h>
32
33void ll_emma2rh_sw_irq_enable(int reg);
34void ll_emma2rh_sw_irq_disable(int reg);
35void ll_emma2rh_gpio_irq_enable(int reg);
36void ll_emma2rh_gpio_irq_disable(int reg);
37
38static void emma2rh_sw_irq_enable(unsigned int irq)
39{
40 ll_emma2rh_sw_irq_enable(irq - EMMA2RH_SW_IRQ_BASE);
41}
42
43static void emma2rh_sw_irq_disable(unsigned int irq)
44{
45 ll_emma2rh_sw_irq_disable(irq - EMMA2RH_SW_IRQ_BASE);
46}
47
48struct irq_chip emma2rh_sw_irq_controller = {
49 .name = "emma2rh_sw_irq",
50 .ack = emma2rh_sw_irq_disable,
51 .mask = emma2rh_sw_irq_disable,
52 .mask_ack = emma2rh_sw_irq_disable,
53 .unmask = emma2rh_sw_irq_enable,
54};
55
56void emma2rh_sw_irq_init(void)
57{
58 u32 i;
59
60 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
61 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
62 &emma2rh_sw_irq_controller,
63 handle_level_irq);
64}
65
66void ll_emma2rh_sw_irq_enable(int irq)
67{
68 u32 reg;
69
70 db_assert(irq >= 0);
71 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
72
73 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
74 reg |= 1 << irq;
75 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
76}
77
78void ll_emma2rh_sw_irq_disable(int irq)
79{
80 u32 reg;
81
82 db_assert(irq >= 0);
83 db_assert(irq < 32);
84
85 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
86 reg &= ~(1 << irq);
87 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
88}
89
90static void emma2rh_gpio_irq_enable(unsigned int irq)
91{
92 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
93}
94
95static void emma2rh_gpio_irq_disable(unsigned int irq)
96{
97 ll_emma2rh_gpio_irq_disable(irq - EMMA2RH_GPIO_IRQ_BASE);
98}
99
100static void emma2rh_gpio_irq_ack(unsigned int irq)
101{
102 irq -= EMMA2RH_GPIO_IRQ_BASE;
103 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
104 ll_emma2rh_gpio_irq_disable(irq);
105}
106
107static void emma2rh_gpio_irq_end(unsigned int irq)
108{
109 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
110 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
111}
112
113struct irq_chip emma2rh_gpio_irq_controller = {
114 .name = "emma2rh_gpio_irq",
115 .ack = emma2rh_gpio_irq_ack,
116 .mask = emma2rh_gpio_irq_disable,
117 .mask_ack = emma2rh_gpio_irq_ack,
118 .unmask = emma2rh_gpio_irq_enable,
119 .end = emma2rh_gpio_irq_end,
120};
121
122void emma2rh_gpio_irq_init(void)
123{
124 u32 i;
125
126 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
127 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
128 &emma2rh_gpio_irq_controller);
129}
130
131void ll_emma2rh_gpio_irq_enable(int irq)
132{
133 u32 reg;
134
135 db_assert(irq >= 0);
136 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
137
138 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
139 reg |= 1 << irq;
140 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
141}
142
143void ll_emma2rh_gpio_irq_disable(int irq)
144{
145 u32 reg;
146
147 db_assert(irq >= 0);
148 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
149
150 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
151 reg &= ~(1 << irq);
152 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
153}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 01:45:24 -0500