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authorThomas Gleixner <tglx@linutronix.de>2011-03-23 17:08:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-03-25 13:45:15 -0400
commit009c200a66a27c34c92ad02ac8c9758e6d0e34e3 (patch)
tree258cfd096863f5f1cd09b7e0b394522df266fd72 /arch/mips/dec
parent93f293610446f10fd13de9f18b4d0300f0d89279 (diff)
MIPS: DEC: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2178/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/dec')
-rw-r--r--arch/mips/dec/ioasic-irq.c60
-rw-r--r--arch/mips/dec/kn02-irq.c23
2 files changed, 24 insertions, 59 deletions
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index cb41954fc321..8d9a5fc607e4 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -17,80 +17,48 @@
17#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
18#include <asm/dec/ioasic_ints.h> 18#include <asm/dec/ioasic_ints.h>
19 19
20
21static int ioasic_irq_base; 20static int ioasic_irq_base;
22 21
23 22static void unmask_ioasic_irq(struct irq_data *d)
24static inline void unmask_ioasic_irq(unsigned int irq)
25{ 23{
26 u32 simr; 24 u32 simr;
27 25
28 simr = ioasic_read(IO_REG_SIMR); 26 simr = ioasic_read(IO_REG_SIMR);
29 simr |= (1 << (irq - ioasic_irq_base)); 27 simr |= (1 << (d->irq - ioasic_irq_base));
30 ioasic_write(IO_REG_SIMR, simr); 28 ioasic_write(IO_REG_SIMR, simr);
31} 29}
32 30
33static inline void mask_ioasic_irq(unsigned int irq) 31static void mask_ioasic_irq(struct irq_data *d)
34{ 32{
35 u32 simr; 33 u32 simr;
36 34
37 simr = ioasic_read(IO_REG_SIMR); 35 simr = ioasic_read(IO_REG_SIMR);
38 simr &= ~(1 << (irq - ioasic_irq_base)); 36 simr &= ~(1 << (d->irq - ioasic_irq_base));
39 ioasic_write(IO_REG_SIMR, simr); 37 ioasic_write(IO_REG_SIMR, simr);
40} 38}
41 39
42static inline void clear_ioasic_irq(unsigned int irq) 40static void ack_ioasic_irq(struct irq_data *d)
43{ 41{
44 u32 sir; 42 mask_ioasic_irq(d);
45
46 sir = ~(1 << (irq - ioasic_irq_base));
47 ioasic_write(IO_REG_SIR, sir);
48}
49
50static inline void ack_ioasic_irq(unsigned int irq)
51{
52 mask_ioasic_irq(irq);
53 fast_iob(); 43 fast_iob();
54} 44}
55 45
56static inline void end_ioasic_irq(unsigned int irq)
57{
58 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
59 unmask_ioasic_irq(irq);
60}
61
62static struct irq_chip ioasic_irq_type = { 46static struct irq_chip ioasic_irq_type = {
63 .name = "IO-ASIC", 47 .name = "IO-ASIC",
64 .ack = ack_ioasic_irq, 48 .irq_ack = ack_ioasic_irq,
65 .mask = mask_ioasic_irq, 49 .irq_mask = mask_ioasic_irq,
66 .mask_ack = ack_ioasic_irq, 50 .irq_mask_ack = ack_ioasic_irq,
67 .unmask = unmask_ioasic_irq, 51 .irq_unmask = unmask_ioasic_irq,
68}; 52};
69 53
70
71#define unmask_ioasic_dma_irq unmask_ioasic_irq
72
73#define mask_ioasic_dma_irq mask_ioasic_irq
74
75#define ack_ioasic_dma_irq ack_ioasic_irq
76
77static inline void end_ioasic_dma_irq(unsigned int irq)
78{
79 clear_ioasic_irq(irq);
80 fast_iob();
81 end_ioasic_irq(irq);
82}
83
84static struct irq_chip ioasic_dma_irq_type = { 54static struct irq_chip ioasic_dma_irq_type = {
85 .name = "IO-ASIC-DMA", 55 .name = "IO-ASIC-DMA",
86 .ack = ack_ioasic_dma_irq, 56 .irq_ack = ack_ioasic_irq,
87 .mask = mask_ioasic_dma_irq, 57 .irq_mask = mask_ioasic_irq,
88 .mask_ack = ack_ioasic_dma_irq, 58 .irq_mask_ack = ack_ioasic_irq,
89 .unmask = unmask_ioasic_dma_irq, 59 .irq_unmask = unmask_ioasic_irq,
90 .end = end_ioasic_dma_irq,
91}; 60};
92 61
93
94void __init init_ioasic_irqs(int base) 62void __init init_ioasic_irqs(int base)
95{ 63{
96 int i; 64 int i;
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index ed90a8deabcc..ef31d98c4fb8 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -27,43 +27,40 @@
27 */ 27 */
28u32 cached_kn02_csr; 28u32 cached_kn02_csr;
29 29
30
31static int kn02_irq_base; 30static int kn02_irq_base;
32 31
33 32static void unmask_kn02_irq(struct irq_data *d)
34static inline void unmask_kn02_irq(unsigned int irq)
35{ 33{
36 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
37 KN02_CSR); 35 KN02_CSR);
38 36
39 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); 37 cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
40 *csr = cached_kn02_csr; 38 *csr = cached_kn02_csr;
41} 39}
42 40
43static inline void mask_kn02_irq(unsigned int irq) 41static void mask_kn02_irq(struct irq_data *d)
44{ 42{
45 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
46 KN02_CSR); 44 KN02_CSR);
47 45
48 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); 46 cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
49 *csr = cached_kn02_csr; 47 *csr = cached_kn02_csr;
50} 48}
51 49
52static void ack_kn02_irq(unsigned int irq) 50static void ack_kn02_irq(struct irq_data *d)
53{ 51{
54 mask_kn02_irq(irq); 52 mask_kn02_irq(d);
55 iob(); 53 iob();
56} 54}
57 55
58static struct irq_chip kn02_irq_type = { 56static struct irq_chip kn02_irq_type = {
59 .name = "KN02-CSR", 57 .name = "KN02-CSR",
60 .ack = ack_kn02_irq, 58 .irq_ack = ack_kn02_irq,
61 .mask = mask_kn02_irq, 59 .irq_mask = mask_kn02_irq,
62 .mask_ack = ack_kn02_irq, 60 .irq_mask_ack = ack_kn02_irq,
63 .unmask = unmask_kn02_irq, 61 .irq_unmask = unmask_kn02_irq,
64}; 62};
65 63
66
67void __init init_kn02_irqs(int base) 64void __init init_kn02_irqs(int base)
68{ 65{
69 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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