aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/dec/time.c
diff options
context:
space:
mode:
authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2008-04-24 23:11:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-04-28 12:14:32 -0400
commit6457d9fc3bb87c72db03cfb34cd414c8fb9b8edf (patch)
treebaf16332ea9bb5734985bb9bc3357b992b32238c /arch/mips/dec/time.c
parent4247417d8457b326ede001cb74af8570b5aa302b (diff)
[MIPS] DS1287: Add clockevent driver
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/dec/time.c')
-rw-r--r--arch/mips/dec/time.c69
1 files changed, 22 insertions, 47 deletions
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 0cbab8d0052b..3965fda94a89 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -9,30 +9,15 @@
9 * 9 *
10 */ 10 */
11#include <linux/bcd.h> 11#include <linux/bcd.h>
12#include <linux/errno.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/mc146818rtc.h> 13#include <linux/mc146818rtc.h>
17#include <linux/mm.h>
18#include <linux/module.h>
19#include <linux/param.h> 14#include <linux/param.h>
20#include <linux/sched.h>
21#include <linux/string.h>
22#include <linux/time.h>
23#include <linux/types.h>
24
25#include <asm/bootinfo.h>
26#include <asm/cpu.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/mipsregs.h>
30#include <asm/sections.h>
31#include <asm/time.h>
32 15
16#include <asm/cpu-features.h>
17#include <asm/ds1287.h>
18#include <asm/time.h>
33#include <asm/dec/interrupts.h> 19#include <asm/dec/interrupts.h>
34#include <asm/dec/ioasic.h> 20#include <asm/dec/ioasic.h>
35#include <asm/dec/ioasic_addrs.h>
36#include <asm/dec/machtype.h> 21#include <asm/dec/machtype.h>
37 22
38unsigned long read_persistent_clock(void) 23unsigned long read_persistent_clock(void)
@@ -139,42 +124,32 @@ int rtc_mips_set_mmss(unsigned long nowtime)
139 return retval; 124 return retval;
140} 125}
141 126
142static int dec_timer_state(void) 127void __init plat_time_init(void)
143{ 128{
144 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; 129 u32 start, end;
145} 130 int i = HZ / 10;
146 131
147static void dec_timer_ack(void) 132 /* Set up the rate of periodic DS1287 interrupts. */
148{ 133 ds1287_set_base_clock(HZ);
149 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */
150}
151 134
152static cycle_t dec_ioasic_hpt_read(void) 135 if (cpu_has_counter) {
153{ 136 while (!ds1287_timer_state())
154 /* 137 ;
155 * The free-running counter is 32-bit which is good for about
156 * 2 minutes, 50 seconds at possible count rates of up to 25MHz.
157 */
158 return ioasic_read(IO_REG_FCTR);
159}
160 138
139 start = read_c0_count();
161 140
162void __init plat_time_init(void) 141 while (i--)
163{ 142 while (!ds1287_timer_state())
164 mips_timer_ack = dec_timer_ack; 143 ;
144
145 end = read_c0_count();
165 146
166 if (!cpu_has_counter && IOASIC) 147 mips_hpt_frequency = (end - start) * 10;
148 printk(KERN_INFO "MIPS counter frequency %dHz\n",
149 mips_hpt_frequency);
150 } else if (IOASIC)
167 /* For pre-R4k systems we use the I/O ASIC's counter. */ 151 /* For pre-R4k systems we use the I/O ASIC's counter. */
168 dec_ioasic_clocksource_init(); 152 dec_ioasic_clocksource_init();
169 153
170 /* Set up the rate of periodic DS1287 interrupts. */ 154 ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
171 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
172}
173
174void __init plat_timer_setup(struct irqaction *irq)
175{
176 setup_irq(dec_interrupt[DEC_IRQ_RTC], irq);
177
178 /* Enable periodic DS1287 interrupts. */
179 CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
180} 155}