[MIPS] Define MIPS_CPU_IRQ_BASE in generic header

The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index d34032ac492a..1058e2f409bb 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -234,7 +234,7 @@ static void __init dec_init_kn01(void)
         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
                 sizeof(kn01_cpu_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
 
 }                               /* dec_init_kn01 */
 
@@ -309,7 +309,7 @@ static void __init dec_init_kn230(void)
         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
                 sizeof(kn230_cpu_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
 
 }                               /* dec_init_kn230 */
 
@@ -403,7 +403,7 @@ static void __init dec_init_kn02(void)
         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
                 sizeof(kn02_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_kn02_irqs(KN02_IRQ_BASE);
 
 }                               /* dec_init_kn02 */
@@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void)
         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
                 sizeof(kn02ba_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_ioasic_irqs(IO_IRQ_BASE);
 
 }                               /* dec_init_kn02ba */
@@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void)
         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
                 sizeof(kn02ca_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_ioasic_irqs(IO_IRQ_BASE);
 
 }                               /* dec_init_kn02ca */
@@ -702,7 +702,7 @@ static void __init dec_init_kn03(void)
         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
                 sizeof(kn03_asic_mask_nr_tbl));
 
-        mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
+        mips_cpu_irq_init();
         init_ioasic_irqs(IO_IRQ_BASE);
 
 }                               /* dec_init_kn03 */