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authorMaciej W. Rozycki <macro@linux-mips.org>2005-06-22 16:56:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:30 -0400
commit64dac503e8265007ea5c53b4d6bf42488a8a8d7a (patch)
treed086e5ddd6d36118b476ed0fe01091d9d4d70cec /arch/mips/dec/ecc-berr.c
parent3b2396d972ce030e942fef9fcbea1e411b1a62db (diff)
System-specific handling of bus errors for DECstation variations
supporting parity errors only for memory (Pmax/3min/Maxine). Fixes for resources decoded by the KN04/KN05 MB ASIC. Additional clean-ups for the ECC handler. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/dec/ecc-berr.c')
-rw-r--r--arch/mips/dec/ecc-berr.c31
1 files changed, 16 insertions, 15 deletions
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index a36503c95bbb..8f3498aa43ab 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -6,7 +6,7 @@
6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), 6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
7 * 5900/260 (KN05) systems. 7 * 5900/260 (KN05) systems.
8 * 8 *
9 * Copyright (c) 2003 Maciej W. Rozycki 9 * Copyright (c) 2003, 2005 Maciej W. Rozycki
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License 12 * modify it under the terms of the GNU General Public License
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/spinlock.h> 21#include <linux/spinlock.h>
@@ -57,7 +58,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
57 58
58 const char *kind, *agent, *cycle, *event; 59 const char *kind, *agent, *cycle, *event;
59 const char *status = "", *xbit = "", *fmt = ""; 60 const char *status = "", *xbit = "", *fmt = "";
60 dma_addr_t address; 61 unsigned long address;
61 u16 syn = 0, sngl; 62 u16 syn = 0, sngl;
62 63
63 int i = 0; 64 int i = 0;
@@ -66,7 +67,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66 u32 chksyn = *kn0x_chksyn; 67 u32 chksyn = *kn0x_chksyn;
67 int action = MIPS_BE_FATAL; 68 int action = MIPS_BE_FATAL;
68 69
69 /* For non-ECC ack ASAP, so any subsequent errors get caught. */ 70 /* For non-ECC ack ASAP, so that any subsequent errors get caught. */
70 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) 71 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
71 dec_ecc_be_ack(); 72 dec_ecc_be_ack();
72 73
@@ -74,7 +75,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
74 75
75 if (!(erraddr & KN0X_EAR_VALID)) { 76 if (!(erraddr & KN0X_EAR_VALID)) {
76 /* No idea what happened. */ 77 /* No idea what happened. */
77 printk(KERN_ALERT "Unidentified bus error %s.\n", kind); 78 printk(KERN_ALERT "Unidentified bus error %s\n", kind);
78 return action; 79 return action;
79 } 80 }
80 81
@@ -126,7 +127,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
126 /* Ack now, no rewrite will happen. */ 127 /* Ack now, no rewrite will happen. */
127 dec_ecc_be_ack(); 128 dec_ecc_be_ack();
128 129
129 fmt = KERN_ALERT "%s" "invalid.\n"; 130 fmt = KERN_ALERT "%s" "invalid\n";
130 } else { 131 } else {
131 sngl = syn & KN0X_ESR_SNGLO; 132 sngl = syn & KN0X_ESR_SNGLO;
132 syn &= KN0X_ESR_SYNLO; 133 syn &= KN0X_ESR_SYNLO;
@@ -161,12 +162,12 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
161 if (syn == 0x01) { 162 if (syn == 0x01) {
162 fmt = KERN_ALERT "%s" 163 fmt = KERN_ALERT "%s"
163 "%#04x -- %s bit error " 164 "%#04x -- %s bit error "
164 "at check bit C%s.\n"; 165 "at check bit C%s\n";
165 xbit = "X"; 166 xbit = "X";
166 } else { 167 } else {
167 fmt = KERN_ALERT "%s" 168 fmt = KERN_ALERT "%s"
168 "%#04x -- %s bit error " 169 "%#04x -- %s bit error "
169 "at check bit C%s%u.\n"; 170 "at check bit C%s%u\n";
170 } 171 }
171 i = syn >> 2; 172 i = syn >> 2;
172 } else { 173 } else {
@@ -176,16 +177,16 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
176 if (i < 32) 177 if (i < 32)
177 fmt = KERN_ALERT "%s" 178 fmt = KERN_ALERT "%s"
178 "%#04x -- %s bit error " 179 "%#04x -- %s bit error "
179 "at data bit D%s%u.\n"; 180 "at data bit D%s%u\n";
180 else 181 else
181 fmt = KERN_ALERT "%s" 182 fmt = KERN_ALERT "%s"
182 "%#04x -- %s bit error.\n"; 183 "%#04x -- %s bit error\n";
183 } 184 }
184 } 185 }
185 } 186 }
186 187
187 if (action != MIPS_BE_FIXUP) 188 if (action != MIPS_BE_FIXUP)
188 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n", 189 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
189 kind, agent, cycle, event, address); 190 kind, agent, cycle, event, address);
190 191
191 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR) 192 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
@@ -207,8 +208,8 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
207 return IRQ_HANDLED; 208 return IRQ_HANDLED;
208 209
209 /* 210 /*
210 * FIXME: Find affected processes and kill them, otherwise we 211 * FIXME: Find the affected processes and kill them, otherwise
211 * must die. 212 * we must die.
212 * 213 *
213 * The interrupt is asynchronously delivered thus EPC and RA 214 * The interrupt is asynchronously delivered thus EPC and RA
214 * may be irrelevant, but are printed for a reference. 215 * may be irrelevant, but are printed for a reference.
@@ -235,7 +236,7 @@ static inline void dec_kn02_be_init(void)
235 spin_lock_irqsave(&kn02_lock, flags); 236 spin_lock_irqsave(&kn02_lock, flags);
236 237
237 /* Preset write-only bits of the Control Register cache. */ 238 /* Preset write-only bits of the Control Register cache. */
238 cached_kn02_csr = *csr | KN03_CSR_LEDS; 239 cached_kn02_csr = *csr | KN02_CSR_LEDS;
239 240
240 /* Set normal ECC detection and generation. */ 241 /* Set normal ECC detection and generation. */
241 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); 242 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
@@ -250,7 +251,7 @@ static inline void dec_kn02_be_init(void)
250static inline void dec_kn03_be_init(void) 251static inline void dec_kn03_be_init(void)
251{ 252{
252 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); 253 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);
253 volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); 254 volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
254 255
255 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 256 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
256 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 257 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
@@ -265,7 +266,7 @@ static inline void dec_kn03_be_init(void)
265 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | 266 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
266 KN03_MCR_CORRECT; 267 KN03_MCR_CORRECT;
267 if (current_cpu_data.cputype == CPU_R4400SC) 268 if (current_cpu_data.cputype == CPU_R4400SC)
268 *mbcs |= KN05_MB_CSR_EE; 269 *mbcs |= KN4K_MB_CSR_EE;
269 fast_iob(); 270 fast_iob();
270} 271}
271 272