litmus-rt.git - The LITMUS^RT kernel.

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author	Maciej W. Rozycki <macro@linux-mips.org>	2005-06-22 16:56:26 -0400
committer	Ralf Baechle <ralf@linux-mips.org>	2005-10-29 14:31:30 -0400
commit	64dac503e8265007ea5c53b4d6bf42488a8a8d7a (patch)
tree	d086e5ddd6d36118b476ed0fe01091d9d4d70cec /arch/mips/dec/Makefile
parent	3b2396d972ce030e942fef9fcbea1e411b1a62db (diff)

System-specific handling of bus errors for DECstation variations

supporting parity errors only for memory (Pmax/3min/Maxine). Fixes for resources decoded by the KN04/KN05 MB ASIC. Additional clean-ups for the ECC handler. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Diffstat (limited to 'arch/mips/dec/Makefile')

-rw-r--r--

arch/mips/dec/Makefile

1 files changed, 2 insertions, 2 deletions


diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile index 688757a97cb8..ed181fdc3ac9 100644 --- a/arch/mips/dec/Makefile +++ b/arch/mips/dec/Makefile
@@ -2,8 +2,8 @@
2	# Makefile for the DECstation family specific parts of the kernel	2	# Makefile for the DECstation family specific parts of the kernel
3	#	3	#
4		4
5	obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \	5	obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
6	setup.o time.o	6	kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
7		7
8	obj-$(CONFIG_PROM_CONSOLE) += promcon.o	8	obj-$(CONFIG_PROM_CONSOLE) += promcon.o
9	obj-$(CONFIG_CPU_HAS_WB) += wbflush.o	9	obj-$(CONFIG_CPU_HAS_WB) += wbflush.o

/*====================================================================== Device driver for Intel 82365 and compatible PC Card controllers. i82365.c 1.265 1999/11/10 18:36:21 The contents of this file are subject to the Mozilla Public License Version 1.1 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.mozilla.org/MPL/ Software distributed under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for the specific language governing rights and limitations under the License. The initial developer of the original code is David A. Hinds <dahinds@users.sourceforge.net>. Portions created by David A. Hinds are Copyright (C) 1999 David A. Hinds. All Rights Reserved. Alternatively, the contents of this file may be used under the terms of the GNU General Public License version 2 (the "GPL"), in which case the provisions of the GPL are applicable instead of the above. If you wish to allow the use of your version of this file only under the terms of the GPL and not to allow others to use your version of this file under the MPL, indicate your decision by deleting the provisions above and replace them with the notice and other provisions required by the GPL. If you do not delete the provisions above, a recipient may use your version of this file under either the MPL or the GPL. ======================================================================*/ #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/init.h> #include <linux/types.h> #include <linux/fcntl.h> #include <linux/string.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/timer.h> #include <linux/ioport.h> #include <linux/delay.h> #include <linux/workqueue.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/bitops.h> #include <asm/irq.h> #include <asm/io.h> #include <asm/system.h> #include <pcmcia/ss.h> #include <linux/isapnp.h> /* ISA-bus controllers */ #include "i82365.h" #include "cirrus.h" #include "vg468.h" #include "ricoh.h" static irqreturn_t i365_count_irq(int, void *); static inline int _check_irq(int irq, int flags) { if (request_irq(irq, i365_count_irq, flags, "x", i365_count_irq) != 0) return -1; free_irq(irq, i365_count_irq); return 0; } /*====================================================================*/ /* Parameters that can be set with 'insmod' */ /* Default base address for i82365sl and other ISA chips */ static unsigned long i365_base = 0x3e0; /* Should we probe at 0x3e2 for an extra ISA controller? */ static int extra_sockets = 0; /* Specify a socket number to ignore */ static int ignore = -1; /* Bit map or list of interrupts to choose from */ static u_int irq_mask = 0xffff; static int irq_list[16]; static unsigned int irq_list_count; /* The card status change interrupt -- 0 means autoselect */ static int cs_irq = 0; /* Probe for safe interrupts? */ static int do_scan = 1; /* Poll status interval -- 0 means default to interrupt */ static int poll_interval = 0; /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ static int cycle_time = 120; /* Cirrus options */ static int has_dma = -1; static int has_led = -1; static int has_ring = -1; static int dynamic_mode = 0; static int freq_bypass = -1; static int setup_time = -1; static int cmd_time = -1; static int recov_time = -1; /* Vadem options */ static int async_clock = -1; static int cable_mode = -1; static int wakeup = 0; module_param(i365_base, ulong, 0444); module_param(ignore, int, 0444); module_param(extra_sockets, int, 0444); module_param(irq_mask, int, 0444); module_param_array(irq_list, int, &irq_list_count, 0444); module_param(cs_irq, int, 0444); module_param(async_clock, int, 0444); module_param(cable_mode, int, 0444); module_param(wakeup, int, 0444); module_param(do_scan, int, 0444); module_param(poll_interval, int, 0444); module_param(cycle_time, int, 0444); module_param(has_dma, int, 0444); module_param(has_led, int, 0444); module_param(has_ring, int, 0444); module_param(dynamic_mode, int, 0444); module_param(freq_bypass, int, 0444); module_param(setup_time, int, 0444); module_param(cmd_time, int, 0444); module_param(recov_time, int, 0444); /*====================================================================*/ typedef struct cirrus_state_t { u_char misc1, misc2; u_char timer[6]; } cirrus_state_t; typedef struct vg46x_state_t { u_char ctl, ema; } vg46x_state_t; struct i82365_socket { u_short type, flags; struct pcmcia_socket socket; unsigned int number; unsigned int ioaddr; u_short psock; u_char cs_irq, intr; union { cirrus_state_t cirrus; vg46x_state_t vg46x; } state; }; /* Where we keep track of our sockets... */ static int sockets = 0; static struct i82365_socket socket[8] = { { 0, }, /* ... */ }; /* Default ISA interrupt mask */ #define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */ static int grab_irq; static DEFINE_SPINLOCK(isa_lock); #define ISA_LOCK(n, f) spin_lock_irqsave(&isa_lock, f) #define ISA_UNLOCK(n, f) spin_unlock_irqrestore(&isa_lock, f) static struct timer_list poll_timer; /*====================================================================*/ /* These definitions must match the pcic table! */ typedef enum pcic_id { IS_I82365A, IS_I82365B, IS_I82365DF, IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469, IS_PD6710, IS_PD672X, IS_VT83C469, } pcic_id; /* Flags for classifying groups of controllers */ #define IS_VADEM 0x0001 #define IS_CIRRUS 0x0002 #define IS_VIA 0x0010 #define IS_UNKNOWN 0x0400 #define IS_VG_PWR 0x0800 #define IS_DF_PWR 0x1000 #define IS_REGISTERED 0x2000 #define IS_ALIVE 0x8000 typedef struct pcic_t { char *name; u_short flags; } pcic_t; static pcic_t pcic[] = { { "Intel i82365sl A step", 0 }, { "Intel i82365sl B step", 0 }, { "Intel i82365sl DF", IS_DF_PWR }, { "IBM Clone", 0 }, { "Ricoh RF5C296/396", 0 }, { "VLSI 82C146", 0 }, { "Vadem VG-468", IS_VADEM }, { "Vadem VG-469", IS_VADEM|IS_VG_PWR }, { "Cirrus PD6710", IS_CIRRUS }, { "Cirrus PD672x", IS_CIRRUS }, { "VIA VT83C469", IS_CIRRUS|IS_VIA }, }; #define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t)) /*====================================================================*/ static DEFINE_SPINLOCK(bus_lock); static u_char i365_get(u_short sock, u_short reg) { unsigned long flags; spin_lock_irqsave(&bus_lock,flags); { unsigned int port = socket[sock].ioaddr; u_char val; reg = I365_REG(socket[sock].psock, reg); outb(reg, port); val = inb(port+1); spin_unlock_irqrestore(&bus_lock,flags); return val; } } static void i365_set(u_short sock, u_short reg, u_char data) { unsigned long flags; spin_lock_irqsave(&bus_lock,flags); { unsigned int port = socket[sock].ioaddr; u_char val = I365_REG(socket[sock].psock, reg); outb(val, port); outb(data, port+1); spin_unlock_irqrestore(&bus_lock,flags); } } static void i365_bset(u_short sock, u_short reg, u_char mask) { u_char d = i365_get(sock, reg); d |= mask; i365_set(sock, reg, d); } static void i365_bclr(u_short sock, u_short reg, u_char mask) { u_char d = i365_get(sock, reg); d &= ~mask; i365_set(sock, reg, d); } static void i365_bflip(u_short sock, u_short reg, u_char mask, int b) { u_char d = i365_get(sock, reg); if (b) d |= mask; else d &= ~mask; i365_set(sock, reg, d); } static u_short i365_get_pair(u_short sock, u_short reg) { u_short a, b; a = i365_get(sock, reg); b = i365_get(sock, reg+1); return (a + (b<<8)); } static void i365_set_pair(u_short sock, u_short reg, u_short data) { i365_set(sock, reg, data & 0xff); i365_set(sock, reg+1, data >> 8); } /*====================================================================== Code to save and restore global state information for Cirrus PD67xx controllers, and to set and report global configuration options. The VIA controllers also use these routines, as they are mostly Cirrus lookalikes, without the timing registers. ======================================================================*/ #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) static void cirrus_get_state(u_short s) { int i; cirrus_state_t *p = &socket[s].state.cirrus; p->misc1 = i365_get(s, PD67_MISC_CTL_1); p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); p->misc2 = i365_get(s, PD67_MISC_CTL_2); for (i = 0; i < 6; i++) p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i); } static void cirrus_set_state(u_short s) { int i; u_char misc; cirrus_state_t *p = &socket[s].state.cirrus; misc = i365_get(s, PD67_MISC_CTL_2); i365_set(s, PD67_MISC_CTL_2, p->misc2); if (misc & PD67_MC2_SUSPEND) mdelay(50); misc = i365_get(s, PD67_MISC_CTL_1); misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); i365_set(s, PD67_MISC_CTL_1, misc | p->misc1); for (i = 0; i < 6; i++) i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]); } static u_int __init cirrus_set_opts(u_short s, char *buf) { struct i82365_socket *t = &socket[s]; cirrus_state_t *p = &socket[s].state.cirrus; u_int mask = 0xffff; if (has_ring == -1) has_ring = 1; flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring); flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); if (p->misc2 & PD67_MC2_IRQ15_RI) strcat(buf, " [ring]"); if (p->misc2 & PD67_MC2_DYNAMIC_MODE) strcat(buf, " [dyn mode]"); if (p->misc2 & PD67_MC2_FREQ_BYPASS) strcat(buf, " [freq bypass]"); if (p->misc1 & PD67_MC1_INPACK_ENA) strcat(buf, " [inpack]"); if (p->misc2 & PD67_MC2_IRQ15_RI) mask &= ~0x8000; if (has_led > 0) { strcat(buf, " [led]"); mask &= ~0x1000; } if (has_dma > 0) { strcat(buf, " [dma]"); mask &= ~0x0600; } if (!(t->flags & IS_VIA)) { if (setup_time >= 0) p->timer[0] = p->timer[3] = setup_time; if (cmd_time > 0) { p->timer[1] = cmd_time; p->timer[4] = cmd_time*2+4; } if (p->timer[1] == 0) { p->timer[1] = 6; p->timer[4] = 16; if (p->timer[0] == 0) p->timer[0] = p->timer[3] = 1; } if (recov_time >= 0) p->timer[2] = p->timer[5] = recov_time; buf += strlen(buf); sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1], p->timer[2], p->timer[3], p->timer[4], p->timer[5]); } return mask; } /*====================================================================== Code to save and restore global state information for Vadem VG468 and VG469 controllers, and to set and report global configuration options. ======================================================================*/ static void vg46x_get_state(u_short s) { vg46x_state_t *p = &socket[s].state.vg46x; p->ctl = i365_get(s, VG468_CTL); if (socket[s].type == IS_VG469) p->ema = i365_get(s, VG469_EXT_MODE); } static void vg46x_set_state(u_short s) { vg46x_state_t *p = &socket[s].state.vg46x; i365_set(s, VG468_CTL, p->ctl); if (socket[s].type == IS_VG469) i365_set(s, VG469_EXT_MODE, p->ema); } static u_int __init vg46x_set_opts(u_short s, char *buf) { vg46x_state_t *p = &socket[s].state.vg46x; flip(p->ctl, VG468_CTL_ASYNC, async_clock); flip(p->ema, VG469_MODE_CABLE, cable_mode); if (p->ctl & VG468_CTL_ASYNC) strcat(buf, " [async]"); if (p->ctl & VG468_CTL_INPACK) strcat(buf, " [inpack]"); if (socket[s].type == IS_VG469) { u_char vsel = i365_get(s, VG469_VSELECT); if (vsel & VG469_VSEL_EXT_STAT) { strcat(buf, " [ext mode]"); if (vsel & VG469_VSEL_EXT_BUS) strcat(buf, " [isa buf]"); } if (p->ema & VG469_MODE_CABLE) strcat(buf, " [cable]"); if (p->ema & VG469_MODE_COMPAT) strcat(buf, " [c step]"); } return 0xffff; } /*====================================================================== Generic routines to get and set controller options ======================================================================*/ static void get_bridge_state(u_short s) { struct i82365_socket *t = &socket[s]; if (t->flags & IS_CIRRUS) cirrus_get_state(s); else if (t->flags & IS_VADEM) vg46x_get_state(s); } static void set_bridge_state(u_short s) { struct i82365_socket *t = &socket[s]; if (t->flags & IS_CIRRUS) cirrus_set_state(s); else { i365_set(s, I365_GBLCTL, 0x00); i365_set(s, I365_GENCTL, 0x00); } i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr); if (t->flags & IS_VADEM) vg46x_set_state(s); } static u_int __init set_bridge_opts(u_short s, u_short ns) { u_short i; u_int m = 0xffff; char buf[128]; for (i = s; i < s+ns; i++) { if (socket[i].flags & IS_ALIVE) { printk(KERN_INFO " host opts [%d]: already alive!\n", i); continue; } buf[0] = '\0'; get_bridge_state(i); if (socket[i].flags & IS_CIRRUS) m = cirrus_set_opts(i, buf); else if (socket[i].flags & IS_VADEM) m = vg46x_set_opts(i, buf); set_bridge_state(i); printk(KERN_INFO " host opts [%d]:%s\n", i, (*buf) ? buf : " none"); } return m; } /*====================================================================== Interrupt testing code, for ISA and PCI interrupts ======================================================================*/ static volatile u_int irq_hits; static u_short irq_sock; static irqreturn_t i365_count_irq(int irq, void *dev) { i365_get(irq_sock, I365_CSC); irq_hits++; pr_debug("i82365: -> hit on irq %d\n", irq); return IRQ_HANDLED; } static u_int __init test_irq(u_short sock, int irq) { pr_debug("i82365: testing ISA irq %d\n", irq); if (request_irq(irq, i365_count_irq, IRQF_PROBE_SHARED, "scan", i365_count_irq) != 0) return 1; irq_hits = 0; irq_sock = sock; msleep(10); if (irq_hits) { free_irq(irq, i365_count_irq); pr_debug("i82365: spurious hit!\n"); return 1; } /* Generate one interrupt */ i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (irq << 4)); i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ); udelay(1000); free_irq(irq, i365_count_irq); /* mask all interrupts */ i365_set(sock, I365_CSCINT, 0); pr_debug("i82365: hits = %d\n", irq_hits); return (irq_hits != 1); } static u_int __init isa_scan(u_short sock, u_int mask0) { u_int mask1 = 0; int i; #ifdef __alpha__ #define PIC 0x4d0 /* Don't probe level-triggered interrupts -- reserved for PCI */ mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8)); #endif if (do_scan) { set_bridge_state(sock); i365_set(sock, I365_CSCINT, 0); for (i = 0; i < 16; i++) if ((mask0 & (1 << i)) && (test_irq(sock, i) == 0)) mask1 |= (1 << i); for (i = 0; i < 16; i++) if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0)) mask1 ^= (1 << i); } printk(KERN_INFO " ISA irqs ("); if (mask1) { printk("scanned"); } else { /* Fallback: just find interrupts that aren't in use */ for (i = 0; i < 16; i++) if ((mask0 & (1 << i)) && (_check_irq(i, IRQF_PROBE_SHARED) == 0)) mask1 |= (1 << i); printk("default"); /* If scan failed, default to polled status */ if (!cs_irq && (poll_interval == 0)) poll_interval = HZ; } printk(") = "); for (i = 0; i < 16; i++) if (mask1 & (1<<i)) printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); if (mask1 == 0) printk("none!"); return mask1; } /*====================================================================*/ /* Time conversion functions */ static int to_cycles(int ns) { return ns/cycle_time; } /*====================================================================*/ static int __init identify(unsigned int port, u_short sock) { u_char val; int type = -1; /* Use the next free entry in the socket table */ socket[sockets].ioaddr = port; socket[sockets].psock = sock; /* Wake up a sleepy Cirrus controller */ if (wakeup) { i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND); /* Pause at least 50 ms */ mdelay(50); } if ((val = i365_get(sockets, I365_IDENT)) & 0x70) return -1; switch (val) { case 0x82: type = IS_I82365A; break; case 0x83: type = IS_I82365B; break; case 0x84: type = IS_I82365DF; break; case 0x88: case 0x89: case 0x8a: type = IS_IBM; break; } /* Check for Vadem VG-468 chips */ outb(0x0e, port); outb(0x37, port); i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV); val = i365_get(sockets, I365_IDENT); if (val & I365_IDENT_VADEM) { i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV); type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468; } /* Check for Ricoh chips */ val = i365_get(sockets, RF5C_CHIP_ID); if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396)) type = IS_RF5Cx96; /* Check for Cirrus CL-PD67xx chips */ i365_set(sockets, PD67_CHIP_INFO, 0); val = i365_get(sockets, PD67_CHIP_INFO); if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { val = i365_get(sockets, PD67_CHIP_INFO); if ((val & PD67_INFO_CHIP_ID) == 0) { type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; i365_set(sockets, PD67_EXT_INDEX, 0xe5);


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