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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-07-30 09:40:35 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-31 16:35:34 -0400
commitff32b062ea6d16a1c53d57da0ac9419c9d015534 (patch)
treec206f1e32f6b10149924fc48d359574b90410cb3 /arch/mips/ddb5xxx
parent796756bab6fd09111159b76288169e18fa13d3e8 (diff)
[MIPS] DDB5477: Remove support
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ddb5xxx')
-rw-r--r--arch/mips/ddb5xxx/Kconfig4
-rw-r--r--arch/mips/ddb5xxx/common/Makefile7
-rw-r--r--arch/mips/ddb5xxx/common/nile4.c130
-rw-r--r--arch/mips/ddb5xxx/common/prom.c132
-rw-r--r--arch/mips/ddb5xxx/common/rtc_ds1386.c170
-rw-r--r--arch/mips/ddb5xxx/ddb5477/Makefile11
-rw-r--r--arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c49
-rw-r--r--arch/mips/ddb5xxx/ddb5477/debug.c160
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c209
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c154
-rw-r--r--arch/mips/ddb5xxx/ddb5477/kgdb_io.c136
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.c96
-rw-r--r--arch/mips/ddb5xxx/ddb5477/lcd44780.h15
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c399
14 files changed, 0 insertions, 1672 deletions
diff --git a/arch/mips/ddb5xxx/Kconfig b/arch/mips/ddb5xxx/Kconfig
deleted file mode 100644
index e9b5de49f4c2..000000000000
--- a/arch/mips/ddb5xxx/Kconfig
+++ /dev/null
@@ -1,4 +0,0 @@
1config DDB5477_BUS_FREQUENCY
2 int "bus frequency (in kHZ, 0 for auto-detect)"
3 depends on DDB5477
4 default 0
diff --git a/arch/mips/ddb5xxx/common/Makefile b/arch/mips/ddb5xxx/common/Makefile
deleted file mode 100644
index 2a6a4e91991c..000000000000
--- a/arch/mips/ddb5xxx/common/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for the common code of NEC DDB-Vrc5xxx board
3#
4
5obj-y += nile4.o prom.o rtc_ds1386.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ddb5xxx/common/nile4.c b/arch/mips/ddb5xxx/common/nile4.c
deleted file mode 100644
index 7ec7d903ba97..000000000000
--- a/arch/mips/ddb5xxx/common/nile4.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * arch/mips/ddb5xxx/common/nile4.c
7 * misc low-level routines for vrc-5xxx controllers.
8 *
9 * derived from original code by Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18
19#include <asm/ddb5xxx/ddb5xxx.h>
20
21u32
22ddb_calc_pdar(u32 phys, u32 size, int width,
23 int on_memory_bus, int pci_visible)
24{
25 u32 maskbits;
26 u32 widthbits;
27
28 switch (size) {
29#if 0 /* We don't support 4 GB yet */
30 case 0x100000000: /* 4 GB */
31 maskbits = 4;
32 break;
33#endif
34 case 0x80000000: /* 2 GB */
35 maskbits = 5;
36 break;
37 case 0x40000000: /* 1 GB */
38 maskbits = 6;
39 break;
40 case 0x20000000: /* 512 MB */
41 maskbits = 7;
42 break;
43 case 0x10000000: /* 256 MB */
44 maskbits = 8;
45 break;
46 case 0x08000000: /* 128 MB */
47 maskbits = 9;
48 break;
49 case 0x04000000: /* 64 MB */
50 maskbits = 10;
51 break;
52 case 0x02000000: /* 32 MB */
53 maskbits = 11;
54 break;
55 case 0x01000000: /* 16 MB */
56 maskbits = 12;
57 break;
58 case 0x00800000: /* 8 MB */
59 maskbits = 13;
60 break;
61 case 0x00400000: /* 4 MB */
62 maskbits = 14;
63 break;
64 case 0x00200000: /* 2 MB */
65 maskbits = 15;
66 break;
67 case 0: /* OFF */
68 maskbits = 0;
69 break;
70 default:
71 panic("nile4_set_pdar: unsupported size %p", (void *) size);
72 }
73 switch (width) {
74 case 8:
75 widthbits = 0;
76 break;
77 case 16:
78 widthbits = 1;
79 break;
80 case 32:
81 widthbits = 2;
82 break;
83 case 64:
84 widthbits = 3;
85 break;
86 default:
87 panic("nile4_set_pdar: unsupported width %d", width);
88 }
89
90 return maskbits | (on_memory_bus ? 0x10 : 0) |
91 (pci_visible ? 0x20 : 0) | (widthbits << 6) |
92 (phys & 0xffe00000);
93}
94
95void
96ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
97 int on_memory_bus, int pci_visible)
98{
99 u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible);
100 ddb_out32(pdar, temp);
101 ddb_out32(pdar + 4, 0);
102
103 /*
104 * When programming a PDAR, the register should be read immediately
105 * after writing it. This ensures that address decoders are properly
106 * configured.
107 * [jsun] is this really necessary?
108 */
109 ddb_in32(pdar);
110 ddb_in32(pdar + 4);
111}
112
113/*
114 * routines that mess with PCIINITx registers
115 */
116
117void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
118{
119 switch (type) {
120 case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */
121 case DDB_PCICMD_IO: /* PCI I/O Space */
122 case DDB_PCICMD_MEM: /* PCI Memory Space */
123 case DDB_PCICMD_CFG: /* PCI Configuration Space */
124 break;
125 default:
126 panic("nile4_set_pmr: invalid type %d", type);
127 }
128 ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
129 ddb_out32(pmr + 4, 0);
130}
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
deleted file mode 100644
index 54a857b5e3ba..000000000000
--- a/arch/mips/ddb5xxx/common/prom.c
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/sched.h>
13#include <linux/bootmem.h>
14
15#include <asm/addrspace.h>
16#include <asm/bootinfo.h>
17#include <asm/ddb5xxx/ddb5xxx.h>
18#include <asm/debug.h>
19
20const char *get_system_type(void)
21{
22 switch (mips_machtype) {
23 case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477";
24 case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper";
25 case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII";
26 default: return "Unknown NEC board";
27 }
28}
29
30#if defined(CONFIG_DDB5477)
31void ddb5477_runtime_detection(void);
32#endif
33
34/* [jsun@junsun.net] PMON passes arguments in C main() style */
35void __init prom_init(void)
36{
37 int argc = fw_arg0;
38 char **arg = (char**) fw_arg1;
39 int i;
40
41 /* if user passes kernel args, ignore the default one */
42 if (argc > 1)
43 arcs_cmdline[0] = '\0';
44
45 /* arg[0] is "g", the rest is boot parameters */
46 for (i = 1; i < argc; i++) {
47 if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
48 >= sizeof(arcs_cmdline))
49 break;
50 strcat(arcs_cmdline, arg[i]);
51 strcat(arcs_cmdline, " ");
52 }
53
54 mips_machgroup = MACH_GROUP_NEC_DDB;
55
56#if defined(CONFIG_DDB5477)
57 ddb5477_runtime_detection();
58 add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
59#endif
60}
61
62void __init prom_free_prom_memory(void)
63{
64}
65
66#if defined(CONFIG_DDB5477)
67
68#define DEFAULT_LCS1_BASE 0x19000000
69#define TESTVAL1 'K'
70#define TESTVAL2 'S'
71
72int board_ram_size;
73void ddb5477_runtime_detection(void)
74{
75 volatile char *test_offset;
76 char saved_test_byte;
77
78 /* Determine if this is a DDB5477 board, or a BSB-VR0300
79 base board. We can tell by checking for the location of
80 the NVRAM. It lives at the beginning of LCS1 on the DDB5477,
81 and the beginning of LCS1 on the BSB-VR0300 is flash memory.
82 The first 2K of the NVRAM are reserved, so don't we'll poke
83 around just after that.
84 */
85
86 /* We can only use the PCI bus to distinquish between
87 the Rockhopper and RockhopperII backplanes and this must
88 wait until ddb5477_board_init() in setup.c after the 5477
89 is initialized. So, until then handle
90 both Rockhopper and RockhopperII backplanes as Rockhopper 1
91 */
92
93 test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800);
94 saved_test_byte = *test_offset;
95
96 *test_offset = TESTVAL1;
97 if (*test_offset != TESTVAL1) {
98 /* We couldn't set our test value, so it must not be NVRAM,
99 so it's a BSB_VR0300 */
100 mips_machtype = MACH_NEC_ROCKHOPPER;
101 } else {
102 /* We may have gotten lucky, and the TESTVAL1 was already
103 stored at the test location, so we must check a second
104 test value */
105 *test_offset = TESTVAL2;
106 if (*test_offset != TESTVAL2) {
107 /* OK, we couldn't set this value either, so it must
108 definately be a BSB_VR0300 */
109 mips_machtype = MACH_NEC_ROCKHOPPER;
110 } else {
111 /* We could change the value twice, so it must be
112 NVRAM, so it's a DDB_VRC5477 */
113 mips_machtype = MACH_NEC_DDB5477;
114 }
115 }
116 /* Restore the original byte */
117 *test_offset = saved_test_byte;
118
119 /* before we know a better way, we will trust PMON for getting
120 * RAM size
121 */
122 board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf));
123
124 db_run(printk("DDB run-time detection : %s, %d MB RAM\n",
125 mips_machtype == MACH_NEC_DDB5477 ?
126 "DDB5477" : "Rockhopper",
127 board_ram_size >> 20));
128
129 /* we can't handle ram size > 128 MB */
130 db_assert(board_ram_size <= (128 << 20));
131}
132#endif
diff --git a/arch/mips/ddb5xxx/common/rtc_ds1386.c b/arch/mips/ddb5xxx/common/rtc_ds1386.c
deleted file mode 100644
index 5dc34daa7150..000000000000
--- a/arch/mips/ddb5xxx/common/rtc_ds1386.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/common/rtc_ds1386.c
6 * low-level RTC hookups for s for Dallas 1396 chip.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14
15/*
16 * This file exports a function, rtc_ds1386_init(), which expects an
17 * uncached base address as the argument. It will set the two function
18 * pointers expected by the MIPS generic timer code.
19 */
20
21#include <linux/types.h>
22#include <linux/time.h>
23#include <linux/bcd.h>
24
25#include <asm/time.h>
26#include <asm/addrspace.h>
27
28#include <asm/mc146818rtc.h>
29#include <asm/debug.h>
30
31#define EPOCH 2000
32
33#define READ_RTC(x) *(volatile unsigned char*)(rtc_base+x)
34#define WRITE_RTC(x, y) *(volatile unsigned char*)(rtc_base+x) = y
35
36static unsigned long rtc_base;
37
38static unsigned long
39rtc_ds1386_get_time(void)
40{
41 u8 byte;
42 u8 temp;
43 unsigned int year, month, day, hour, minute, second;
44 unsigned long flags;
45
46 spin_lock_irqsave(&rtc_lock, flags);
47 /* let us freeze external registers */
48 byte = READ_RTC(0xB);
49 byte &= 0x3f;
50 WRITE_RTC(0xB, byte);
51
52 /* read time data */
53 year = BCD2BIN(READ_RTC(0xA)) + EPOCH;
54 month = BCD2BIN(READ_RTC(0x9) & 0x1f);
55 day = BCD2BIN(READ_RTC(0x8));
56 minute = BCD2BIN(READ_RTC(0x2));
57 second = BCD2BIN(READ_RTC(0x1));
58
59 /* hour is special - deal with it later */
60 temp = READ_RTC(0x4);
61
62 /* enable time transfer */
63 byte |= 0x80;
64 WRITE_RTC(0xB, byte);
65 spin_unlock_irqrestore(&rtc_lock, flags);
66
67 /* calc hour */
68 if (temp & 0x40) {
69 /* 12 hour format */
70 hour = BCD2BIN(temp & 0x1f);
71 if (temp & 0x20) hour += 12; /* PM */
72 } else {
73 /* 24 hour format */
74 hour = BCD2BIN(temp & 0x3f);
75 }
76
77 return mktime(year, month, day, hour, minute, second);
78}
79
80static int
81rtc_ds1386_set_time(unsigned long t)
82{
83 struct rtc_time tm;
84 u8 byte;
85 u8 temp;
86 u8 year, month, day, hour, minute, second;
87 unsigned long flags;
88
89 spin_lock_irqsave(&rtc_lock, flags);
90 /* let us freeze external registers */
91 byte = READ_RTC(0xB);
92 byte &= 0x3f;
93 WRITE_RTC(0xB, byte);
94
95 /* convert */
96 to_tm(t, &tm);
97
98
99 /* check each field one by one */
100 year = BIN2BCD(tm.tm_year - EPOCH);
101 if (year != READ_RTC(0xA)) {
102 WRITE_RTC(0xA, year);
103 }
104
105 temp = READ_RTC(0x9);
106 month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */
107 if (month != (temp & 0x1f)) {
108 WRITE_RTC( 0x9,
109 (month & 0x1f) | (temp & ~0x1f) );
110 }
111
112 day = BIN2BCD(tm.tm_mday);
113 if (day != READ_RTC(0x8)) {
114 WRITE_RTC(0x8, day);
115 }
116
117 temp = READ_RTC(0x4);
118 if (temp & 0x40) {
119 /* 12 hour format */
120 hour = 0x40;
121 if (tm.tm_hour > 12) {
122 hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f);
123 } else {
124 hour |= BIN2BCD(tm.tm_hour);
125 }
126 } else {
127 /* 24 hour format */
128 hour = BIN2BCD(tm.tm_hour) & 0x3f;
129 }
130 if (hour != temp) WRITE_RTC(0x4, hour);
131
132 minute = BIN2BCD(tm.tm_min);
133 if (minute != READ_RTC(0x2)) {
134 WRITE_RTC(0x2, minute);
135 }
136
137 second = BIN2BCD(tm.tm_sec);
138 if (second != READ_RTC(0x1)) {
139 WRITE_RTC(0x1, second);
140 }
141 spin_unlock_irqrestore(&rtc_lock, flags);
142
143 return 0;
144}
145
146void
147rtc_ds1386_init(unsigned long base)
148{
149 unsigned char byte;
150
151 /* remember the base */
152 rtc_base = base;
153 db_assert((rtc_base & 0xe0000000) == KSEG1);
154
155 /* turn on RTC if it is not on */
156 byte = READ_RTC(0x9);
157 if (byte & 0x80) {
158 byte &= 0x7f;
159 WRITE_RTC(0x9, byte);
160 }
161
162 /* enable time transfer */
163 byte = READ_RTC(0xB);
164 byte |= 0x80;
165 WRITE_RTC(0xB, byte);
166
167 /* set the function pointers */
168 rtc_mips_get_time = rtc_ds1386_get_time;
169 rtc_mips_set_time = rtc_ds1386_set_time;
170}
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile
deleted file mode 100644
index 520094405905..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for NEC DDB-Vrc5477 board
3#
4
5obj-y += ddb5477-platform.o irq.o irq_5477.o setup.o \
6 lcd44780.o
7
8obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
9obj-$(CONFIG_KGDB) += kgdb_io.o
10
11EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c b/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
deleted file mode 100644
index c16020ad54c2..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/serial_8250.h>
11
12#include <asm/ddb5xxx/ddb5477.h>
13
14#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
15
16#define DDB5477_PORT(base, int) \
17{ \
18 .mapbase = base, \
19 .irq = int, \
20 .uartclk = 1843200, \
21 .iotype = UPIO_MEM, \
22 .flags = DDB_UART_FLAGS, \
23 .regshift = 3, \
24}
25
26static struct plat_serial8250_port uart8250_data[] = {
27 DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0),
28 DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1),
29 { },
30};
31
32static struct platform_device uart8250_device = {
33 .name = "serial8250",
34 .id = PLAT8250_DEV_PLATFORM,
35 .dev = {
36 .platform_data = uart8250_data,
37 },
38};
39
40static int __init uart8250_init(void)
41{
42 return platform_device_register(&uart8250_device);
43}
44
45module_init(uart8250_init);
46
47MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477");
diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c
deleted file mode 100644
index 68919d5f8ffd..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/debug.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * arch/mips/ddb5xxx/ddb5477/debug.c
7 * vrc5477 specific debug routines.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 ***********************************************************************
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/mipsregs.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22typedef struct {
23 const char *regname;
24 unsigned regaddr;
25} Register;
26
27void jsun_show_regs(char *name, Register *regs)
28{
29 int i;
30
31 printk("\nshow regs: %s\n", name);
32 for(i=0;regs[i].regname!= NULL; i++) {
33 printk("%-16s= %08x\t\t(@%08x)\n",
34 regs[i].regname,
35 *(unsigned *)(regs[i].regaddr),
36 regs[i].regaddr);
37 }
38}
39
40static Register int_regs[] = {
41 {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
42 {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
43 {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
44 {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
45 {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
46 {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
47 {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
48 {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
49 {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
50 {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
51 {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
52 {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
53 {NULL, 0x0}
54};
55
56void vrc5477_show_int_regs()
57{
58 jsun_show_regs("interrupt registers", int_regs);
59 printk("CPU CAUSE = %08x\n", read_c0_cause());
60 printk("CPU STATUS = %08x\n", read_c0_status());
61}
62static Register pdar_regs[] = {
63 {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
64 {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
65 {"DDB_LCS0", DDB_BASE + DDB_LCS0},
66 {"DDB_LCS1", DDB_BASE + DDB_LCS1},
67 {"DDB_LCS2", DDB_BASE + DDB_LCS2},
68 {"DDB_INTCS", DDB_BASE + DDB_INTCS},
69 {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
70 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
71 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
72 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
73 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
74 {NULL, 0x0}
75};
76void vrc5477_show_pdar_regs(void)
77{
78 jsun_show_regs("PDAR regs", pdar_regs);
79}
80
81static Register bar_regs[] = {
82 {"DDB_BARC0", DDB_BASE + DDB_BARC0},
83 {"DDB_BARM010", DDB_BASE + DDB_BARM010},
84 {"DDB_BARM230", DDB_BASE + DDB_BARM230},
85 {"DDB_BAR00", DDB_BASE + DDB_BAR00},
86 {"DDB_BAR10", DDB_BASE + DDB_BAR10},
87 {"DDB_BAR20", DDB_BASE + DDB_BAR20},
88 {"DDB_BAR30", DDB_BASE + DDB_BAR30},
89 {"DDB_BAR40", DDB_BASE + DDB_BAR40},
90 {"DDB_BAR50", DDB_BASE + DDB_BAR50},
91 {"DDB_BARB0", DDB_BASE + DDB_BARB0},
92 {"DDB_BARC1", DDB_BASE + DDB_BARC1},
93 {"DDB_BARM011", DDB_BASE + DDB_BARM011},
94 {"DDB_BARM231", DDB_BASE + DDB_BARM231},
95 {"DDB_BAR01", DDB_BASE + DDB_BAR01},
96 {"DDB_BAR11", DDB_BASE + DDB_BAR11},
97 {"DDB_BAR21", DDB_BASE + DDB_BAR21},
98 {"DDB_BAR31", DDB_BASE + DDB_BAR31},
99 {"DDB_BAR41", DDB_BASE + DDB_BAR41},
100 {"DDB_BAR51", DDB_BASE + DDB_BAR51},
101 {"DDB_BARB1", DDB_BASE + DDB_BARB1},
102 {NULL, 0x0}
103};
104void vrc5477_show_bar_regs(void)
105{
106 jsun_show_regs("BAR regs", bar_regs);
107}
108
109static Register pci_regs[] = {
110 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
111 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
112 {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
113 {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
114 {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
115 {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
116 {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
117 {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
118 {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
119 {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
120 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
121 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
122 {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
123 {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
124 {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
125 {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
126 {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
127 {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
128 {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
129 {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
130 {NULL, 0x0}
131};
132void vrc5477_show_pci_regs(void)
133{
134 jsun_show_regs("PCI regs", pci_regs);
135}
136
137static Register lb_regs[] = {
138 {"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
139 {"DDB_LCST0", DDB_BASE + DDB_LCST0},
140 {"DDB_LCST1", DDB_BASE + DDB_LCST1},
141 {"DDB_LCST2", DDB_BASE + DDB_LCST2},
142 {"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
143 {"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
144 {"DDB_BTM", DDB_BASE + DDB_BTM},
145 {"DDB_BCST", DDB_BASE + DDB_BCST},
146 {NULL, 0x0}
147};
148void vrc5477_show_lb_regs(void)
149{
150 jsun_show_regs("Local Bus regs", lb_regs);
151}
152
153void vrc5477_show_all_regs(void)
154{
155 vrc5477_show_pdar_regs();
156 vrc5477_show_pci_regs();
157 vrc5477_show_bar_regs();
158 vrc5477_show_int_regs();
159 vrc5477_show_lb_regs();
160}
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
deleted file mode 100644
index faa4a506bf82..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/irq.c
6 * The irq setup and misc routines for DDB5476.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18
19#include <asm/i8259.h>
20#include <asm/irq_cpu.h>
21#include <asm/system.h>
22#include <asm/mipsregs.h>
23#include <asm/debug.h>
24#include <asm/addrspace.h>
25#include <asm/bootinfo.h>
26
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29
30/*
31 * IRQ mapping
32 *
33 * 0-7: 8 CPU interrupts
34 * 0 - software interrupt 0
35 * 1 - software interrupt 1
36 * 2 - most Vrc5477 interrupts are routed to this pin
37 * 3 - (optional) some other interrupts routed to this pin for debugg
38 * 4 - not used
39 * 5 - not used
40 * 6 - not used
41 * 7 - cpu timer (used by default)
42 *
43 * 8-39: 32 Vrc5477 interrupt sources
44 * (refer to the Vrc5477 manual)
45 */
46
47#define PCI0 DDB_INTPPES0
48#define PCI1 DDB_INTPPES1
49
50#define ACTIVE_LOW 1
51#define ACTIVE_HIGH 0
52
53#define LEVEL_SENSE 2
54#define EDGE_TRIGGER 0
55
56#define INTA 0
57#define INTB 1
58#define INTC 2
59#define INTD 3
60#define INTE 4
61
62static inline void
63set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
64{
65 u32 reg_value;
66 u32 reg_bitmask;
67
68 reg_value = ddb_in32(pci);
69 reg_bitmask = 0x3 << (intn * 2);
70
71 reg_value &= ~reg_bitmask;
72 reg_value |= (active | trigger) << (intn * 2);
73 ddb_out32(pci, reg_value);
74}
75
76extern void vrc5477_irq_init(u32 base);
77static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
78
79void __init arch_init_irq(void)
80{
81 /* by default, we disable all interrupts and route all vrc5477
82 * interrupts to pin 0 (irq 2) */
83 ddb_out32(DDB_INTCTRL0, 0);
84 ddb_out32(DDB_INTCTRL1, 0);
85 ddb_out32(DDB_INTCTRL2, 0);
86 ddb_out32(DDB_INTCTRL3, 0);
87
88 clear_c0_status(0xff00);
89 set_c0_status(0x0400);
90
91 /* setup PCI interrupt attributes */
92 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
93 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
94 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
95 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
96 else
97 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
98 set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
99 set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
100
101 set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
102 set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
103 set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
104 set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
105 set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
106
107 /*
108 * for debugging purpose, we enable several error interrupts
109 * and route them to pin 1. (IP3)
110 */
111 /* cpu parity check - 0 */
112 ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
113 /* cpu no-target decode - 1 */
114 ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
115 /* local bus read time-out - 7 */
116 ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
117 /* PCI SERR# - 14 */
118 ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
119 /* PCI internal error - 15 */
120 ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
121 /* IOPCI SERR# - 30 */
122 ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
123 /* IOPCI internal error - 31 */
124 ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
125
126 /* init all controllers */
127 init_i8259_irqs();
128 mips_cpu_irq_init();
129 vrc5477_irq_init(VRC5477_IRQ_BASE);
130
131
132 /* setup cascade interrupts */
133 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
134 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
135}
136
137u8 i8259_interrupt_ack(void)
138{
139 u8 irq;
140 u32 reg;
141
142 /* Set window 0 for interrupt acknowledge */
143 reg = ddb_in32(DDB_PCIINIT10);
144
145 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
146 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
147 ddb_out32(DDB_PCIINIT10, reg);
148
149 return irq;
150}
151/*
152 * the first level int-handler will jump here if it is a vrc5477 irq
153 */
154#define NUM_5477_IRQS 32
155static void vrc5477_irq_dispatch(void)
156{
157 u32 intStatus;
158 u32 bitmask;
159 u32 i;
160
161 db_assert(ddb_in32(DDB_INT2STAT) == 0);
162 db_assert(ddb_in32(DDB_INT3STAT) == 0);
163 db_assert(ddb_in32(DDB_INT4STAT) == 0);
164 db_assert(ddb_in32(DDB_NMISTAT) == 0);
165
166 if (ddb_in32(DDB_INT1STAT) != 0) {
167#if defined(CONFIG_RUNTIME_DEBUG)
168 vrc5477_show_int_regs();
169#endif
170 panic("error interrupt has happened.");
171 }
172
173 intStatus = ddb_in32(DDB_INT0STAT);
174
175 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
176 /* check for i8259 interrupts */
177 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
178 int i8259_irq = i8259_interrupt_ack();
179 do_IRQ(i8259_irq);
180 return;
181 }
182 }
183
184 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
185 /* do we need to "and" with the int mask? */
186 if (intStatus & bitmask) {
187 do_IRQ(VRC5477_IRQ_BASE + i);
188 return;
189 }
190 }
191}
192
193#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
194
195asmlinkage void plat_irq_dispatch(void)
196{
197 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
198
199 if (pending & STATUSF_IP7)
200 do_IRQ(CPU_IRQ_BASE + 7);
201 else if (pending & VR5477INTS)
202 vrc5477_irq_dispatch();
203 else if (pending & STATUSF_IP0)
204 do_IRQ(CPU_IRQ_BASE);
205 else if (pending & STATUSF_IP1)
206 do_IRQ(CPU_IRQ_BASE + 1);
207 else
208 spurious_interrupt();
209}
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
deleted file mode 100644
index 98c3b15eb369..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5477/irq_5477.c
6 * This file defines the irq handler for Vrc5477.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15/*
16 * Vrc5477 defines 32 IRQs.
17 *
18 * This file exports one function:
19 * vrc5477_irq_init(u32 irq_base);
20 */
21
22#include <linux/interrupt.h>
23#include <linux/types.h>
24#include <linux/ptrace.h>
25
26#include <asm/debug.h>
27
28#include <asm/ddb5xxx/ddb5xxx.h>
29
30/* number of total irqs supported by Vrc5477 */
31#define NUM_5477_IRQ 32
32
33static int vrc5477_irq_base = -1;
34
35
36static void
37vrc5477_irq_enable(unsigned int irq)
38{
39 db_assert(vrc5477_irq_base != -1);
40 db_assert(irq >= vrc5477_irq_base);
41 db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
42
43 ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
44}
45
46static void
47vrc5477_irq_disable(unsigned int irq)
48{
49 db_assert(vrc5477_irq_base != -1);
50 db_assert(irq >= vrc5477_irq_base);
51 db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
52
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54}
55
56static void
57vrc5477_irq_ack(unsigned int irq)
58{
59 db_assert(vrc5477_irq_base != -1);
60 db_assert(irq >= vrc5477_irq_base);
61 db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
62
63 /* clear the interrupt bit */
64 /* some irqs require the driver to clear the sources */
65 ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
66
67 /* disable interrupt - some handler will re-enable the irq
68 * and if the interrupt is leveled, we will have infinite loop
69 */
70 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
71}
72
73static void
74vrc5477_irq_end(unsigned int irq)
75{
76 db_assert(vrc5477_irq_base != -1);
77 db_assert(irq >= vrc5477_irq_base);
78 db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
79
80 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
81 ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
82}
83
84struct irq_chip vrc5477_irq_controller = {
85 .name = "vrc5477_irq",
86 .ack = vrc5477_irq_ack,
87 .mask = vrc5477_irq_disable,
88 .mask_ack = vrc5477_irq_ack,
89 .unmask = vrc5477_irq_enable,
90 .end = vrc5477_irq_end
91};
92
93void __init vrc5477_irq_init(u32 irq_base)
94{
95 u32 i;
96
97 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
98 set_irq_chip(i, &vrc5477_irq_controller);
99
100 vrc5477_irq_base = irq_base;
101}
102
103void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
104{
105 u32 reg_value;
106 u32 reg_bitmask;
107 u32 reg_index;
108
109 db_assert(vrc5477_irq >= 0);
110 db_assert(vrc5477_irq < NUM_5477_IRQ);
111 db_assert(ip >= 0);
112 db_assert((ip < 5) || (ip == 6));
113
114 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
115 reg_value = ddb_in32(reg_index);
116 reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
117 reg_value &= ~reg_bitmask;
118 reg_value |= ip << (vrc5477_irq % 8 * 4);
119 ddb_out32(reg_index, reg_value);
120}
121
122void ll_vrc5477_irq_enable(int vrc5477_irq)
123{
124 u32 reg_value;
125 u32 reg_bitmask;
126 u32 reg_index;
127
128 db_assert(vrc5477_irq >= 0);
129 db_assert(vrc5477_irq < NUM_5477_IRQ);
130
131 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
132 reg_value = ddb_in32(reg_index);
133 reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
134 db_assert((reg_value & reg_bitmask) == 0);
135 ddb_out32(reg_index, reg_value | reg_bitmask);
136}
137
138void ll_vrc5477_irq_disable(int vrc5477_irq)
139{
140 u32 reg_value;
141 u32 reg_bitmask;
142 u32 reg_index;
143
144 db_assert(vrc5477_irq >= 0);
145 db_assert(vrc5477_irq < NUM_5477_IRQ);
146
147 reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
148 reg_value = ddb_in32(reg_index);
149 reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
150
151 /* we assert that the interrupt is enabled (perhaps over-zealous) */
152 db_assert( (reg_value & reg_bitmask) != 0);
153 ddb_out32(reg_index, reg_value & ~reg_bitmask);
154}
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
deleted file mode 100644
index 385bbdb10170..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for DDB5477. We use the second serial port (upper one).
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xbfa04240
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 8
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 0;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up baud rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.c b/arch/mips/ddb5xxx/ddb5477/lcd44780.c
deleted file mode 100644
index 9510b9ae6453..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/lcd44780.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * lcd44780.c
3 * Simple "driver" for a memory-mapped 44780-style LCD display.
4 *
5 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000)
15#define LCD44780_DATA ((volatile unsigned char *)0xbe020001)
16
17#define LCD44780_4BIT_1LINE 0x20
18#define LCD44780_4BIT_2LINE 0x28
19#define LCD44780_8BIT_1LINE 0x30
20#define LCD44780_8BIT_2LINE 0x38
21#define LCD44780_MODE_DEC 0x04
22#define LCD44780_MODE_DEC_SHIFT 0x05
23#define LCD44780_MODE_INC 0x06
24#define LCD44780_MODE_INC_SHIFT 0x07
25#define LCD44780_SCROLL_LEFT 0x18
26#define LCD44780_SCROLL_RIGHT 0x1e
27#define LCD44780_CURSOR_UNDERLINE 0x0e
28#define LCD44780_CURSOR_BLOCK 0x0f
29#define LCD44780_CURSOR_OFF 0x0c
30#define LCD44780_CLEAR 0x01
31#define LCD44780_BLANK 0x08
32#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF
33#define LCD44780_HOME 0x02
34#define LCD44780_LEFT 0x10
35#define LCD44780_RIGHT 0x14
36
37void lcd44780_wait(void)
38{
39 int i, j;
40 for(i=0; i < 400; i++)
41 for(j=0; j < 10000; j++);
42}
43
44void lcd44780_command(unsigned char c)
45{
46 *LCD44780_COMMAND = c;
47 lcd44780_wait();
48}
49
50void lcd44780_data(unsigned char c)
51{
52 *LCD44780_DATA = c;
53 lcd44780_wait();
54}
55
56void lcd44780_puts(const char* s)
57{
58 int j;
59 int pos = 0;
60
61 lcd44780_command(LCD44780_CLEAR);
62 while(*s) {
63 lcd44780_data(*s);
64 s++;
65 pos++;
66 if (pos == 8) {
67 /* We must write 32 of spaces to get cursor to 2nd line */
68 for (j=0; j<32; j++) {
69 lcd44780_data(' ');
70 }
71 }
72 if (pos == 16) {
73 /* We have filled all 16 character positions, so stop
74 outputing data */
75 break;
76 }
77 }
78#ifdef LCD44780_PUTS_PAUSE
79 {
80 int i;
81
82 for(i = 1; i < 2000; i++)
83 lcd44780_wait();
84 }
85#endif
86}
87
88void lcd44780_init(void)
89{
90 // The display on the RockHopper is physically a single
91 // 16 char line (two 8 char lines concatenated). bdl
92 lcd44780_command(LCD44780_8BIT_2LINE);
93 lcd44780_command(LCD44780_MODE_INC);
94 lcd44780_command(LCD44780_CURSOR_BLOCK);
95 lcd44780_command(LCD44780_CLEAR);
96}
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.h b/arch/mips/ddb5xxx/ddb5477/lcd44780.h
deleted file mode 100644
index cf2f0f71eee5..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/lcd44780.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * lcd44780.h
3 * Simple "driver" for a memory-mapped 44780-style LCD display.
4 *
5 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14void lcd44780_puts(const char* s);
15void lcd44780_init(void);
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
deleted file mode 100644
index f0cc0e8a8afa..000000000000
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ /dev/null
@@ -1,399 +0,0 @@
1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * arch/mips/ddb5xxx/ddb5477/setup.c
9 * Setup file for DDB5477.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/sched.h>
20#include <linux/pci.h>
21#include <linux/ide.h>
22#include <linux/irq.h>
23#include <linux/fs.h>
24#include <linux/ioport.h>
25#include <linux/param.h> /* for HZ */
26#include <linux/major.h>
27#include <linux/kdev_t.h>
28#include <linux/root_dev.h>
29#include <linux/pm.h>
30
31#include <asm/cpu.h>
32#include <asm/bootinfo.h>
33#include <asm/addrspace.h>
34#include <asm/time.h>
35#include <asm/bcache.h>
36#include <asm/irq.h>
37#include <asm/reboot.h>
38#include <asm/gdb-stub.h>
39#include <asm/traps.h>
40#include <asm/debug.h>
41
42#include <asm/ddb5xxx/ddb5xxx.h>
43
44#include "lcd44780.h"
45
46
47#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
48
49#define SP_TIMER_BASE DDB_SPT1CTRL_L
50#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
51
52static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
53
54static void ddb_machine_restart(char *command)
55{
56 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
57
58 u32 t;
59
60 /* PCI cold reset */
61 ddb_pci_reset_bus();
62
63 /* CPU cold reset */
64 t = ddb_in32(DDB_CPUSTAT);
65 db_assert((t&1));
66 ddb_out32(DDB_CPUSTAT, t);
67
68 /* Call the PROM */
69 back_to_prom();
70}
71
72static void ddb_machine_halt(void)
73{
74 printk("DDB Vrc-5477 halted.\n");
75 while (1);
76}
77
78static void ddb_machine_power_off(void)
79{
80 printk("DDB Vrc-5477 halted. Please turn off the power.\n");
81 while (1);
82}
83
84extern void rtc_ds1386_init(unsigned long base);
85
86static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
87{
88 unsigned int freq;
89 unsigned char c;
90 unsigned int t1, t2;
91 unsigned i;
92
93 ddb_out32(SP_TIMER_BASE, 0xffffffff);
94 ddb_out32(SP_TIMER_BASE+4, 0x1);
95 ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
96
97 /* check if rtc is running */
98 c= *(volatile unsigned char*)rtc_base;
99 for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
100 if (c == *(volatile unsigned char*)rtc_base) {
101 printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
102 return 83333000;
103 }
104
105 c= *(volatile unsigned char*)rtc_base;
106 while (c == *(volatile unsigned char*)rtc_base);
107 /* we are now at the turn of 1/100th second, if no error. */
108 t1 = ddb_in32(SP_TIMER_BASE+8);
109
110 for (i=0; i< 10; i++) {
111 c= *(volatile unsigned char*)rtc_base;
112 while (c == *(volatile unsigned char*)rtc_base);
113 /* we are now at the turn of another 1/100th second */
114 t2 = ddb_in32(SP_TIMER_BASE+8);
115 }
116
117 ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
118
119 freq = (t1 - t2)*10;
120 printk("DDB bus frequency detection : %u \n", freq);
121 return freq;
122}
123
124static void __init ddb_time_init(void)
125{
126 unsigned long rtc_base;
127 unsigned int i;
128
129 /* we have ds1396 RTC chip */
130 if (mips_machtype == MACH_NEC_ROCKHOPPER
131 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
132 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
133 } else {
134 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
135 }
136 rtc_ds1386_init(rtc_base);
137
138 /* do we need to do run-time detection of bus speed? */
139 if (bus_frequency == 0) {
140 bus_frequency = detect_bus_frequency(rtc_base);
141 }
142
143 /* mips_hpt_frequency is 1/2 of the cpu core freq */
144 i = (read_c0_config() >> 28 ) & 7;
145 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
146 i = 4;
147 mips_hpt_frequency = bus_frequency*(i+4)/4;
148}
149
150void __init plat_timer_setup(struct irqaction *irq)
151{
152#if defined(USE_CPU_COUNTER_TIMER)
153
154 /* we are using the cpu counter for timer interrupts */
155 setup_irq(CPU_IRQ_BASE + 7, irq);
156
157#else
158
159 /* if we use Special purpose timer 1 */
160 ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
161 ddb_out32(SP_TIMER_BASE+4, 0x1);
162 setup_irq(SP_TIMER_IRQ, irq);
163
164#endif
165}
166
167static void ddb5477_board_init(void);
168
169extern struct pci_controller ddb5477_ext_controller;
170extern struct pci_controller ddb5477_io_controller;
171
172void __init plat_mem_setup(void)
173{
174 /* initialize board - we don't trust the loader */
175 ddb5477_board_init();
176
177 set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
178
179 board_time_init = ddb_time_init;
180
181 _machine_restart = ddb_machine_restart;
182 _machine_halt = ddb_machine_halt;
183 pm_power_off = ddb_machine_power_off;
184
185 /* setup resource limits */
186 ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
187 iomem_resource.end = 0xffffffff;
188
189 /* Reboot on panic */
190 panic_timeout = 180;
191
192 register_pci_controller (&ddb5477_ext_controller);
193 register_pci_controller (&ddb5477_io_controller);
194}
195
196static void __init ddb5477_board_init(void)
197{
198 /* ----------- setup PDARs ------------ */
199
200 /* SDRAM should have been set */
201 db_assert(ddb_in32(DDB_SDRAM0) ==
202 ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
203
204 /* SDRAM1 should be turned off. What is this for anyway ? */
205 db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
206
207 /* Setup local bus. */
208
209 /* Flash U12 PDAR and timing. */
210 ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
211 ddb_out32(DDB_LCST0, 0x00090842);
212
213 /* We need to setup LCS1 and LCS2 differently based on the
214 board_version */
215 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
216 /* Flash U13 PDAR and timing. */
217 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
218 ddb_out32(DDB_LCST1, 0x00090842);
219
220 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
221 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
222 } else {
223 /* misc */
224 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
225 /* mezzanie (?) */
226 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
227 }
228
229 /* verify VRC5477 base addr */
230 db_assert(ddb_in32(DDB_VRC5477) ==
231 ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
232
233 /* verify BOOT ROM addr */
234 db_assert(ddb_in32(DDB_BOOTCS) ==
235 ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
236
237 /* setup PCI windows - window0 for MEM/config, window1 for IO */
238 ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
239 ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
240 ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
241 ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
242
243 /* ------------ reset PCI bus and BARs ----------------- */
244 ddb_pci_reset_bus();
245
246 ddb_out32(DDB_BARM010, 0x00000008);
247 ddb_out32(DDB_BARM011, 0x00000008);
248
249 ddb_out32(DDB_BARC0, 0xffffffff);
250 ddb_out32(DDB_BARM230, 0xffffffff);
251 ddb_out32(DDB_BAR00, 0xffffffff);
252 ddb_out32(DDB_BAR10, 0xffffffff);
253 ddb_out32(DDB_BAR20, 0xffffffff);
254 ddb_out32(DDB_BAR30, 0xffffffff);
255 ddb_out32(DDB_BAR40, 0xffffffff);
256 ddb_out32(DDB_BAR50, 0xffffffff);
257 ddb_out32(DDB_BARB0, 0xffffffff);
258
259 ddb_out32(DDB_BARC1, 0xffffffff);
260 ddb_out32(DDB_BARM231, 0xffffffff);
261 ddb_out32(DDB_BAR01, 0xffffffff);
262 ddb_out32(DDB_BAR11, 0xffffffff);
263 ddb_out32(DDB_BAR21, 0xffffffff);
264 ddb_out32(DDB_BAR31, 0xffffffff);
265 ddb_out32(DDB_BAR41, 0xffffffff);
266 ddb_out32(DDB_BAR51, 0xffffffff);
267 ddb_out32(DDB_BARB1, 0xffffffff);
268
269 /*
270 * We use pci master register 0 for memory space / config space
271 * And we use register 1 for IO space.
272 * Note that for memory space, we bump up the pci base address
273 * so that we have 1:1 mapping between PCI memory and cpu physical.
274 * For PCI IO space, it starts from 0 in PCI IO space but with
275 * DDB_xx_IO_BASE in CPU physical address space.
276 */
277 ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
278 DDB_PCI_ACCESS_32);
279 ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
280
281 ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
282 DDB_PCI_ACCESS_32);
283 ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
284 DDB_PCI_ACCESS_32);
285
286
287 /* PCI cross window should be set properly */
288 ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
289 ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
290 ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
291 ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
292
293 if (mips_machtype == MACH_NEC_ROCKHOPPER
294 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
295 /* Disable bus diagnostics. */
296 ddb_out32(DDB_PCICTL0_L, 0);
297 ddb_out32(DDB_PCICTL0_H, 0);
298 ddb_out32(DDB_PCICTL1_L, 0);
299 ddb_out32(DDB_PCICTL1_H, 0);
300 }
301
302 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
303 u16 vid;
304 struct pci_bus bus;
305 struct pci_dev dev_m1533;
306 extern struct pci_ops ddb5477_ext_pci_ops;
307
308 bus.parent = NULL; /* we scan the top level only */
309 bus.ops = &ddb5477_ext_pci_ops;
310 dev_m1533.bus = &bus;
311 dev_m1533.sysdata = NULL;
312 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
313 pci_read_config_word(&dev_m1533, 0, &vid);
314 if (vid == PCI_VENDOR_ID_AL) {
315 printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
316 mips_machtype = MACH_NEC_ROCKHOPPERII;
317 }
318 }
319
320 /* enable USB input buffers */
321 ddb_out32(DDB_PIBMISC, 0x00000007);
322
323 /* For dual-function pins, make them all non-GPIO */
324 ddb_out32(DDB_GIUFUNSEL, 0x0);
325 // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
326
327 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
328
329 /* enable IDE controller on Ali chip (south bridge) */
330 u8 temp8;
331 struct pci_bus bus;
332 struct pci_dev dev_m1533;
333 struct pci_dev dev_m5229;
334 extern struct pci_ops ddb5477_ext_pci_ops;
335
336 /* Setup M1535 registers */
337 bus.parent = NULL; /* we scan the top level only */
338 bus.ops = &ddb5477_ext_pci_ops;
339 dev_m1533.bus = &bus;
340 dev_m1533.sysdata = NULL;
341 dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
342
343 /* setup IDE controller
344 * enable IDE controller (bit 6 - 1)
345 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
346 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
347 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
348 */
349 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
350
351 /*
352 * positive decode (bit6 -0)
353 * enable IDE controler interrupt (bit 4 -1)
354 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
355 */
356 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
357
358 /* Setup M5229 registers */
359 dev_m5229.bus = &bus;
360 dev_m5229.sysdata = NULL;
361 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
362
363 /*
364 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
365 * M5229 IDSEL is addr:15; see above setting
366 */
367 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
368 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
369
370 /*
371 * enable bus master (bit 2) and IO decoding (bit 0)
372 */
373 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
374 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
375
376 /*
377 * enable native, copied from arch/ppc/k2boot/head.S
378 * TODO - need volatile, need to be portable
379 */
380 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
381
382 /* Set Primary Channel Command Block Timing */
383 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
384
385 /*
386 * Enable primary channel 40-pin cable
387 * M5229 register 0x4a (bit 0)
388 */
389 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
390 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
391 }
392
393 if (mips_machtype == MACH_NEC_ROCKHOPPER
394 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
395 printk("lcd44780: initializing\n");
396 lcd44780_init();
397 lcd44780_puts("MontaVista Linux");
398 }
399}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 06:45:36 -0400