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authorRalf Baechle <ralf@linux-mips.org>2006-06-17 23:58:57 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-19 12:39:24 -0400
commiteaff3888742155bd397e45a1c3323c0173042e5b (patch)
treebf8ee6203072e01ce0d50db5898137c7552da6e5 /arch/mips/ddb5xxx
parent2925aba4223f4532e85f0c6f64584b3e0b2849c3 (diff)
[MIPS] Remove support for NEC DDB5074.
As warned several times before. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ddb5xxx')
-rw-r--r--arch/mips/ddb5xxx/common/prom.c5
-rw-r--r--arch/mips/ddb5xxx/ddb5074/Makefile8
-rw-r--r--arch/mips/ddb5xxx/ddb5074/irq.c169
-rw-r--r--arch/mips/ddb5xxx/ddb5074/nile4_pic.c286
-rw-r--r--arch/mips/ddb5xxx/ddb5074/setup.c234
5 files changed, 1 insertions, 701 deletions
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c
index b8d1f7489f3b..18eecbcdfca8 100644
--- a/arch/mips/ddb5xxx/common/prom.c
+++ b/arch/mips/ddb5xxx/common/prom.c
@@ -56,10 +56,7 @@ void __init prom_init(void)
56 56
57 mips_machgroup = MACH_GROUP_NEC_DDB; 57 mips_machgroup = MACH_GROUP_NEC_DDB;
58 58
59#if defined(CONFIG_DDB5074) 59#if defined(CONFIG_DDB5476)
60 mips_machtype = MACH_NEC_DDB5074;
61 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
62#elif defined(CONFIG_DDB5476)
63 mips_machtype = MACH_NEC_DDB5476; 60 mips_machtype = MACH_NEC_DDB5476;
64 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); 61 add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
65#elif defined(CONFIG_DDB5477) 62#elif defined(CONFIG_DDB5477)
diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile
deleted file mode 100644
index 304c02107b46..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
3# under Linux.
4#
5
6obj-y += setup.o irq.o nile4_pic.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c
deleted file mode 100644
index 60c087b7738c..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/irq.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/irq.h>
9#include <linux/signal.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14
15#include <asm/i8259.h>
16#include <asm/io.h>
17#include <asm/irq_cpu.h>
18#include <asm/ptrace.h>
19#include <asm/nile4.h>
20#include <asm/ddb5xxx/ddb5xxx.h>
21#include <asm/ddb5xxx/ddb5074.h>
22
23
24static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
25
26#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
27#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
28#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
29
30#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
31#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
32#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
33
34#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
35#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
36
37#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
38#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
39
40#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
41#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
42
43
44static void m1543_irq_setup(void)
45{
46 /*
47 * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
48 * the possible IO sources in the M1543 are in use by us. We will
49 * use the following mapping:
50 *
51 * IRQ1 - keyboard (default set by M1543)
52 * IRQ3 - reserved for UART B (default set by M1543) (note that
53 * the schematics for the DDB Vrc-5074 board seem to
54 * indicate that IRQ3 is connected to the DS1386
55 * watchdog timer interrupt output so we might have
56 * a conflict)
57 * IRQ4 - reserved for UART A (default set by M1543)
58 * IRQ5 - parallel (default set by M1543)
59 * IRQ8 - DS1386 time of day (RTC) interrupt
60 * IRQ12 - mouse
61 */
62
63 /*
64 * Assing mouse interrupt to IRQ12
65 */
66
67 /* Enter configuration mode */
68 outb(0x51, M1543_PNP_CONFIG);
69 outb(0x23, M1543_PNP_CONFIG);
70
71 /* Select logical device 7 (Keyboard) */
72 outb(0x07, M1543_PNP_INDEX);
73 outb(0x07, M1543_PNP_DATA);
74
75 /* Select IRQ12 */
76 outb(0x72, M1543_PNP_INDEX);
77 outb(0x0c, M1543_PNP_DATA);
78
79 outb(0x30, M1543_PNP_INDEX);
80 printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
81
82 outb(0x70, M1543_PNP_INDEX);
83 printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
84
85 /* Leave configration mode */
86 outb(0xbb, M1543_PNP_CONFIG);
87
88
89}
90
91static void ddb_local0_irqdispatch(struct pt_regs *regs)
92{
93 u32 mask;
94 int nile4_irq;
95
96 mask = nile4_get_irq_stat(0);
97
98 /* Handle the timer interrupt first */
99#if 0
100 if (mask & (1 << NILE4_INT_GPT)) {
101 do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
102 mask &= ~(1 << NILE4_INT_GPT);
103 }
104#endif
105 for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
106 if (mask & 1) {
107 if (nile4_irq == NILE4_INT_INTE) {
108 int i8259_irq;
109
110 nile4_clear_irq(NILE4_INT_INTE);
111 i8259_irq = nile4_i8259_iack();
112 do_IRQ(i8259_irq, regs);
113 } else
114 do_IRQ(nile4_to_irq(nile4_irq), regs);
115
116 }
117}
118
119static void ddb_local1_irqdispatch(void)
120{
121 printk("ddb_local1_irqdispatch called\n");
122}
123
124static void ddb_buserror_irq(void)
125{
126 printk("ddb_buserror_irq called\n");
127}
128
129static void ddb_8254timer_irq(void)
130{
131 printk("ddb_8254timer_irq called\n");
132}
133
134asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
135{
136 unsigned int pending = read_c0_cause() & read_c0_status();
137
138 if (pending & CAUSEF_IP2)
139 ddb_local0_irqdispatch(regs);
140 else if (pending & CAUSEF_IP3)
141 ddb_local1_irqdispatch();
142 else if (pending & CAUSEF_IP6)
143 ddb_buserror_irq();
144 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
145 ddb_8254timer_irq();
146}
147
148void __init arch_init_irq(void)
149{
150 /* setup cascade interrupts */
151 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
152 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
153
154 nile4_irq_setup(NILE4_IRQ_BASE);
155 m1543_irq_setup();
156 init_i8259_irqs();
157
158
159 printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
160
161 mips_cpu_irq_init(CPU_IRQ_BASE);
162
163 printk("enabling 8259 cascade\n");
164
165 ddb5074_led_hex(0);
166
167 /* Enable the interrupt cascade */
168 nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
169}
diff --git a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c b/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
deleted file mode 100644
index 8743ffce8653..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
+++ /dev/null
@@ -1,286 +0,0 @@
1/*
2 * arch/mips/ddb5476/nile4.c --
3 * low-level PIC code for NEC Vrc-5476 (Nile 4)
4 *
5 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
6 * Sony Software Development Center Europe (SDCE), Brussels
7 *
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 *
11 */
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17
18#include <asm/addrspace.h>
19
20#include <asm/ddb5xxx/ddb5xxx.h>
21
22static int irq_base;
23
24/*
25 * Interrupt Programming
26 */
27void nile4_map_irq(int nile4_irq, int cpu_irq)
28{
29 u32 offset, t;
30
31 offset = DDB_INTCTRL;
32 if (nile4_irq >= 8) {
33 offset += 4;
34 nile4_irq -= 8;
35 }
36 t = ddb_in32(offset);
37 t &= ~(7 << (nile4_irq * 4));
38 t |= cpu_irq << (nile4_irq * 4);
39 ddb_out32(offset, t);
40}
41
42void nile4_map_irq_all(int cpu_irq)
43{
44 u32 all, t;
45
46 all = cpu_irq;
47 all |= all << 4;
48 all |= all << 8;
49 all |= all << 16;
50 t = ddb_in32(DDB_INTCTRL);
51 t &= 0x88888888;
52 t |= all;
53 ddb_out32(DDB_INTCTRL, t);
54 t = ddb_in32(DDB_INTCTRL + 4);
55 t &= 0x88888888;
56 t |= all;
57 ddb_out32(DDB_INTCTRL + 4, t);
58}
59
60void nile4_enable_irq(unsigned int nile4_irq)
61{
62 u32 offset, t;
63
64 nile4_irq-=irq_base;
65
66 ddb5074_led_hex(8);
67
68 offset = DDB_INTCTRL;
69 if (nile4_irq >= 8) {
70 offset += 4;
71 nile4_irq -= 8;
72 }
73 ddb5074_led_hex(9);
74 t = ddb_in32(offset);
75 ddb5074_led_hex(0xa);
76 t |= 8 << (nile4_irq * 4);
77 ddb_out32(offset, t);
78 ddb5074_led_hex(0xb);
79}
80
81void nile4_disable_irq(unsigned int nile4_irq)
82{
83 u32 offset, t;
84
85 nile4_irq-=irq_base;
86
87 offset = DDB_INTCTRL;
88 if (nile4_irq >= 8) {
89 offset += 4;
90 nile4_irq -= 8;
91 }
92 t = ddb_in32(offset);
93 t &= ~(8 << (nile4_irq * 4));
94 ddb_out32(offset, t);
95}
96
97void nile4_disable_irq_all(void)
98{
99 ddb_out32(DDB_INTCTRL, 0);
100 ddb_out32(DDB_INTCTRL + 4, 0);
101}
102
103u16 nile4_get_irq_stat(int cpu_irq)
104{
105 return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
106}
107
108void nile4_enable_irq_output(int cpu_irq)
109{
110 u32 t;
111
112 t = ddb_in32(DDB_INTSTAT1 + 4);
113 t |= 1 << (16 + cpu_irq);
114 ddb_out32(DDB_INTSTAT1, t);
115}
116
117void nile4_disable_irq_output(int cpu_irq)
118{
119 u32 t;
120
121 t = ddb_in32(DDB_INTSTAT1 + 4);
122 t &= ~(1 << (16 + cpu_irq));
123 ddb_out32(DDB_INTSTAT1, t);
124}
125
126void nile4_set_pci_irq_polarity(int pci_irq, int high)
127{
128 u32 t;
129
130 t = ddb_in32(DDB_INTPPES);
131 if (high)
132 t &= ~(1 << (pci_irq * 2));
133 else
134 t |= 1 << (pci_irq * 2);
135 ddb_out32(DDB_INTPPES, t);
136}
137
138void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
139{
140 u32 t;
141
142 t = ddb_in32(DDB_INTPPES);
143 if (level)
144 t |= 2 << (pci_irq * 2);
145 else
146 t &= ~(2 << (pci_irq * 2));
147 ddb_out32(DDB_INTPPES, t);
148}
149
150void nile4_clear_irq(int nile4_irq)
151{
152 nile4_irq-=irq_base;
153 ddb_out32(DDB_INTCLR, 1 << nile4_irq);
154}
155
156void nile4_clear_irq_mask(u32 mask)
157{
158 ddb_out32(DDB_INTCLR, mask);
159}
160
161u8 nile4_i8259_iack(void)
162{
163 u8 irq;
164 u32 reg;
165
166 /* Set window 0 for interrupt acknowledge */
167 reg = ddb_in32(DDB_PCIINIT0);
168
169 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
170 irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
171 /* restore window 0 for PCI I/O space */
172 // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
173 ddb_out32(DDB_PCIINIT0, reg);
174
175 /* i8269.c set the base vector to be 0x0 */
176 return irq ;
177}
178
179static unsigned int nile4_irq_startup(unsigned int irq) {
180
181 nile4_enable_irq(irq);
182 return 0;
183
184}
185
186static void nile4_ack_irq(unsigned int irq) {
187
188 ddb5074_led_hex(4);
189
190 nile4_clear_irq(irq);
191 ddb5074_led_hex(2);
192 nile4_disable_irq(irq);
193
194 ddb5074_led_hex(0);
195}
196
197static void nile4_irq_end(unsigned int irq) {
198
199 ddb5074_led_hex(3);
200 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
201 ddb5074_led_hex(5);
202 nile4_enable_irq(irq);
203 ddb5074_led_hex(7);
204 }
205
206 ddb5074_led_hex(1);
207}
208
209#define nile4_irq_shutdown nile4_disable_irq
210
211static hw_irq_controller nile4_irq_controller = {
212 .typename = "nile4",
213 .startup = nile4_irq_startup,
214 .shutdown = nile4_irq_shutdown,
215 .enable = nile4_enable_irq,
216 .disable = nile4_disable_irq,
217 .ack = nile4_ack_irq,
218 .end = nile4_irq_end,
219};
220
221void nile4_irq_setup(u32 base) {
222
223 int i;
224
225 irq_base=base;
226
227 /* Map all interrupts to CPU int #0 */
228 nile4_map_irq_all(0);
229
230 /* PCI INTA#-E# must be level triggered */
231 nile4_set_pci_irq_level_or_edge(0, 1);
232 nile4_set_pci_irq_level_or_edge(1, 1);
233 nile4_set_pci_irq_level_or_edge(2, 1);
234 nile4_set_pci_irq_level_or_edge(3, 1);
235 nile4_set_pci_irq_level_or_edge(4, 1);
236
237 /* PCI INTA#-D# must be active low, INTE# must be active high */
238 nile4_set_pci_irq_polarity(0, 0);
239 nile4_set_pci_irq_polarity(1, 0);
240 nile4_set_pci_irq_polarity(2, 0);
241 nile4_set_pci_irq_polarity(3, 0);
242 nile4_set_pci_irq_polarity(4, 1);
243
244
245 for (i = 0; i < 16; i++) {
246 nile4_clear_irq(i);
247 nile4_disable_irq(i);
248 }
249
250 /* Enable CPU int #0 */
251 nile4_enable_irq_output(0);
252
253 for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
254 irq_desc[i].status = IRQ_DISABLED;
255 irq_desc[i].action = NULL;
256 irq_desc[i].depth = 1;
257 irq_desc[i].handler = &nile4_irq_controller;
258 }
259}
260
261#if defined(CONFIG_RUNTIME_DEBUG)
262void nile4_dump_irq_status(void)
263{
264 printk(KERN_DEBUG "
265 CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
266 (void *) ddb_in32(DDB_CPUSTAT));
267 printk(KERN_DEBUG "
268 INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
269 (void *) ddb_in32(DDB_INTCTRL));
270 printk(KERN_DEBUG
271 "INTSTAT0 = %p:%p\n",
272 (void *) ddb_in32(DDB_INTSTAT0 + 4),
273 (void *) ddb_in32(DDB_INTSTAT0));
274 printk(KERN_DEBUG
275 "INTSTAT1 = %p:%p\n",
276 (void *) ddb_in32(DDB_INTSTAT1 + 4),
277 (void *) ddb_in32(DDB_INTSTAT1));
278 printk(KERN_DEBUG
279 "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
280 (void *) ddb_in32(DDB_INTCLR));
281 printk(KERN_DEBUG
282 "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
283 (void *) ddb_in32(DDB_INTPPES));
284}
285
286#endif
diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c
deleted file mode 100644
index 4882ad1052e7..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/setup.c
+++ /dev/null
@@ -1,234 +0,0 @@
1/*
2 * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7#include <linux/init.h>
8#include <linux/kbd_ll.h>
9#include <linux/kernel.h>
10#include <linux/kdev_t.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18
19#include <asm/addrspace.h>
20#include <asm/bcache.h>
21#include <asm/irq.h>
22#include <asm/reboot.h>
23#include <asm/gdb-stub.h>
24#include <asm/time.h>
25#include <asm/nile4.h>
26#include <asm/ddb5xxx/ddb5074.h>
27#include <asm/ddb5xxx/ddb5xxx.h>
28
29static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
30
31static void ddb_machine_restart(char *command)
32{
33 u32 t;
34
35 /* PCI cold reset */
36 t = nile4_in32(NILE4_PCICTRL + 4);
37 t |= 0x40000000;
38 nile4_out32(NILE4_PCICTRL + 4, t);
39 /* CPU cold reset */
40 t = nile4_in32(NILE4_CPUSTAT);
41 t |= 1;
42 nile4_out32(NILE4_CPUSTAT, t);
43 /* Call the PROM */
44 back_to_prom();
45}
46
47static void ddb_machine_halt(void)
48{
49 printk("DDB Vrc-5074 halted.\n");
50 do {
51 } while (1);
52}
53
54static void ddb_machine_power_off(void)
55{
56 printk("DDB Vrc-5074 halted. Please turn off the power.\n");
57 do {
58 } while (1);
59}
60
61extern void rtc_ds1386_init(unsigned long base);
62
63extern void (*board_timer_setup) (struct irqaction * irq);
64
65static void __init ddb_timer_init(struct irqaction *irq)
66{
67 /* set the clock to 1 Hz */
68 nile4_out32(NILE4_T2CTRL, 1000000);
69 /* enable the General-Purpose Timer */
70 nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
71 /* reset timer */
72 nile4_out32(NILE4_T2CNTR, 0);
73 /* enable interrupt */
74 setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
75 nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
76 change_c0_status(ST0_IM,
77 IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
78
79}
80
81static void __init ddb_time_init(void)
82{
83 /* we have ds1396 RTC chip */
84 rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
85}
86
87
88
89void __init plat_mem_setup(void)
90{
91 set_io_port_base(NILE4_PCI_IO_BASE);
92 isa_slot_offset = NILE4_PCI_MEM_BASE;
93 board_timer_setup = ddb_timer_init;
94 board_time_init = ddb_time_init;
95
96
97 _machine_restart = ddb_machine_restart;
98 _machine_halt = ddb_machine_halt;
99 pm_power_off = ddb_machine_power_off;
100
101 ddb_out32(DDB_BAR0, 0);
102
103 ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
104 ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
105
106 /* Reboot on panic */
107 panic_timeout = 180;
108}
109
110#define USE_NILE4_SERIAL 0
111
112#if USE_NILE4_SERIAL
113#define ns16550_in(reg) nile4_in8((reg)*8)
114#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
115#else
116#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
117static inline u8 ns16550_in(u32 reg)
118{
119 return *(volatile u8 *) (NS16550_BASE + reg);
120}
121
122static inline void ns16550_out(u32 reg, u8 val)
123{
124 *(volatile u8 *) (NS16550_BASE + reg) = val;
125}
126#endif
127
128#define NS16550_RBR 0
129#define NS16550_THR 0
130#define NS16550_DLL 0
131#define NS16550_IER 1
132#define NS16550_DLM 1
133#define NS16550_FCR 2
134#define NS16550_IIR 2
135#define NS16550_LCR 3
136#define NS16550_MCR 4
137#define NS16550_LSR 5
138#define NS16550_MSR 6
139#define NS16550_SCR 7
140
141#define NS16550_LSR_DR 0x01 /* Data ready */
142#define NS16550_LSR_OE 0x02 /* Overrun */
143#define NS16550_LSR_PE 0x04 /* Parity error */
144#define NS16550_LSR_FE 0x08 /* Framing error */
145#define NS16550_LSR_BI 0x10 /* Break */
146#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
147#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
148#define NS16550_LSR_ERR 0x80 /* Error */
149
150
151void _serinit(void)
152{
153#if USE_NILE4_SERIAL
154 ns16550_out(NS16550_LCR, 0x80);
155 ns16550_out(NS16550_DLM, 0x00);
156 ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
157 ns16550_out(NS16550_LCR, 0x00);
158 ns16550_out(NS16550_LCR, 0x03);
159 ns16550_out(NS16550_FCR, 0x47);
160#else
161 /* done by PMON */
162#endif
163}
164
165void _putc(char c)
166{
167 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
168 ns16550_out(NS16550_THR, c);
169 if (c == '\n') {
170 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
171 ns16550_out(NS16550_THR, '\r');
172 }
173}
174
175void _puts(const char *s)
176{
177 char c;
178 while ((c = *s++))
179 _putc(c);
180}
181
182char _getc(void)
183{
184 while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
185 return ns16550_in(NS16550_RBR);
186}
187
188int _testc(void)
189{
190 return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
191}
192
193
194/*
195 * Hexadecimal 7-segment LED
196 */
197void ddb5074_led_hex(int hex)
198{
199 outb(hex, 0x80);
200}
201
202
203/*
204 * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
205 */
206struct pci_dev *pci_pmu = NULL;
207
208void ddb5074_led_d2(int on)
209{
210 u8 t;
211
212 if (pci_pmu) {
213 pci_read_config_byte(pci_pmu, 0x7e, &t);
214 if (on)
215 t &= 0x7f;
216 else
217 t |= 0x80;
218 pci_write_config_byte(pci_pmu, 0x7e, t);
219 }
220}
221
222void ddb5074_led_d3(int on)
223{
224 u8 t;
225
226 if (pci_pmu) {
227 pci_read_config_byte(pci_pmu, 0x7e, &t);
228 if (on)
229 t &= 0xbf;
230 else
231 t |= 0x40;
232 pci_write_config_byte(pci_pmu, 0x7e, t);
233 }
234}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 16:47:41 -0500