Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (22 commits)
  [MIPS] Don't force frame pointers for lockdep on MIPS
  [MIPS] update vr41xx Kconfig
  [MIPS] remove 2 select entries for VR41xx
  [MIPS] rename VR41XX to VR4100 series
  [MIPS] Use DEFINE_SPINLOCK instead of SPIN_LOCK_UNLOCKED.
  [MIPS] Replace old fashioned "__typeof" with "__typeof__".
  [MIPS] Remove unused _THREAD_SIZE_ORDER from asm-offset.c.
  [MIPS] Change PCI host bridge setup/resources
  [MIPS] Register PCI host bridge resource earlier
  [MIPS] Remove pnx8550-v2pci_defconfig
  [MIPS] Add bcm1480 ZBus trace support, fix wait related bugs
  [MIPS] Updated Sibyte headers
  [MIPS] Remove unused argument from kunmap_coherent().
  [MIPS] Malta: Delete unused prototype of mips_timer_interrupt.
  [MIPS] Select ZONE_DMA only if GENERIC_ISA_DMA selected
  [MIPS] MIPS Tech: Get rid of volatile in core code.
  [MIPS] IP22: Get rid of volatile in IP22 core code.
  [MIPS] JMR3927 cleanup
  [MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines
  [MIPS] Cobalt: Split PCI codes from setup.c
  ...

1 files changed, 47 insertions, 0 deletions

diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c
new file mode 100644
index 000000000000..d91027f43de6
--- /dev/null
+++ b/arch/mips/cobalt/pci.c
@@ -0,0 +1,47 @@
+/*
+ * Register PCI controller.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include <asm/gt64120.h>
+
+extern struct pci_ops gt64xxx_pci0_ops;
+
+static struct resource cobalt_mem_resource = {
+        .start  = GT_DEF_PCI0_MEM0_BASE,
+        .end    = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
+        .name   = "PCI memory",
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource cobalt_io_resource = {
+        .start  = 0x1000,
+        .end    = GT_DEF_PCI0_IO_SIZE - 1,
+        .name   = "PCI I/O",
+        .flags  = IORESOURCE_IO,
+};
+
+static struct pci_controller cobalt_pci_controller = {
+        .pci_ops        = &gt64xxx_pci0_ops,
+        .mem_resource   = &cobalt_mem_resource,
+        .io_resource    = &cobalt_io_resource,
+        .io_offset      = 0 - GT_DEF_PCI0_IO_BASE,
+};
+
+static int __init cobalt_pci_init(void)
+{
+        register_pci_controller(&cobalt_pci_controller);
+
+        return 0;
+}
+
+arch_initcall(cobalt_pci_init);