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authorLinus Torvalds <torvalds@linux-foundation.org>2013-03-02 10:44:16 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-03-02 10:44:16 -0500
commitaebb2afd5420c860b7fbc3882a323ef1247fbf16 (patch)
tree05ee0efcebca5ec421de44de7a6d6271088c64a8 /arch/mips/cavium-octeon
parent8eae508b7c6ff502a71d0293b69e97c5505d5840 (diff)
parentedb15d83a875a1f4b1576188844db5c330c3267d (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: o Add basic support for the Mediatek/Ralink Wireless SoC family. o The Qualcomm Atheros platform is extended by support for the new QCA955X SoC series as well as a bunch of patches that get the code ready for OF support. o Lantiq and BCM47XX platform have a few improvements and bug fixes. o MIPS has sent a few patches that get the kernel ready for the upcoming microMIPS support. o The rest of the series is made up of small bug fixes and cleanups that relate to various parts of the MIPS code. The biggy in there is a whitespace cleanup. After I was sent another set of whitespace cleanup patches I decided it was the time to clean the whitespace "issues" for once and and that touches many files below arch/mips/. Fix up silly conflicts, mostly due to whitespace cleanups. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits) MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h MIPS: remove broken conditional inside vpe loader code MIPS: SMTC: fix implicit declaration of set_vi_handler MIPS: early_printk: drop __init annotations MIPS: Probe for and report hardware virtualization support. MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board MIPS: ath79: add USB controller registration code for the QCA955X SoCs MIPS: ath79: add PCI controller registration code for the QCA955X SoCs MIPS: ath79: add WMAC registration code for the QCA955X SoCs MIPS: ath79: register UART for the QCA955X SoCs MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear} MIPS: ath79: add GPIO setup code for the QCA955X SoCs MIPS: ath79: add IRQ handling code for the QCA955X SoCs MIPS: ath79: add clock setup code for the QCA955X SoCs MIPS: ath79: add SoC detection code for the QCA955X SoCs MIPS: ath79: add early printk support for the QCA955X SoCs MIPS: ath79: fix WMAC IRQ resource assignment mips: reserve elfcorehdr mips: Make sure kernel memory is in iomem MIPS: ath79: use dynamically allocated USB platform devices ...
Diffstat (limited to 'arch/mips/cavium-octeon')
-rw-r--r--arch/mips/cavium-octeon/Kconfig9
-rw-r--r--arch/mips/cavium-octeon/Makefile3
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-bootmem.c10
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-board.c28
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c4
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c22
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c4
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-spi.c8
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-util.c34
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c4
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper.c10
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c6
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c66
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-pko.c28
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-spi.c70
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-sysinfo.c16
-rw-r--r--arch/mips/cavium-octeon/oct_ilm.c206
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c4
-rw-r--r--arch/mips/cavium-octeon/octeon-memcpy.S22
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c2
-rw-r--r--arch/mips/cavium-octeon/octeon_3xxx.dts34
-rw-r--r--arch/mips/cavium-octeon/octeon_68xx.dts34
-rw-r--r--arch/mips/cavium-octeon/octeon_boot.h14
-rw-r--r--arch/mips/cavium-octeon/setup.c8
-rw-r--r--arch/mips/cavium-octeon/smp.c10
25 files changed, 436 insertions, 220 deletions
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 2f4f6d5e05b6..75a6df7fd265 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -94,4 +94,13 @@ config SWIOTLB
94 select NEED_SG_DMA_LENGTH 94 select NEED_SG_DMA_LENGTH
95 95
96 96
97config OCTEON_ILM
98 tristate "Module to measure interrupt latency using Octeon CIU Timer"
99 help
100 This driver is a module to measure interrupt latency using the
101 the CIU Timers on Octeon.
102
103 To compile this driver as a module, choose M here. The module
104 will be called octeon-ilm
105
97endif # CPU_CAVIUM_OCTEON 106endif # CPU_CAVIUM_OCTEON
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 6e927cf20df2..3595affb9772 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -17,7 +17,8 @@ obj-y += dma-octeon.o flash_setup.o
17obj-y += octeon-memcpy.o 17obj-y += octeon-memcpy.o
18obj-y += executive/ 18obj-y += executive/
19 19
20obj-$(CONFIG_SMP) += smp.o 20obj-$(CONFIG_SMP) += smp.o
21obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
21 22
22DTS_FILES = octeon_3xxx.dts octeon_68xx.dts 23DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
23DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) 24DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 6d5ddbc112cc..504ed61a47cd 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -155,8 +155,8 @@ int cvmx_bootmem_init(void *mem_desc_ptr)
155 * 155 *
156 * Linux 64 bit: Set XKPHYS bit 156 * Linux 64 bit: Set XKPHYS bit
157 * Linux 32 bit: use mmap to create mapping, use virtual address 157 * Linux 32 bit: use mmap to create mapping, use virtual address
158 * CVMX 64 bit: use physical address directly 158 * CVMX 64 bit: use physical address directly
159 * CVMX 32 bit: use physical address directly 159 * CVMX 32 bit: use physical address directly
160 * 160 *
161 * Note that the CVMX environment assumes the use of 1-1 TLB 161 * Note that the CVMX environment assumes the use of 1-1 TLB
162 * mappings so that the physical addresses can be used 162 * mappings so that the physical addresses can be used
@@ -398,7 +398,7 @@ error_out:
398int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags) 398int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
399{ 399{
400 uint64_t cur_addr; 400 uint64_t cur_addr;
401 uint64_t prev_addr = 0; /* zero is invalid */ 401 uint64_t prev_addr = 0; /* zero is invalid */
402 int retval = 0; 402 int retval = 0;
403 403
404#ifdef DEBUG 404#ifdef DEBUG
@@ -424,7 +424,7 @@ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
424 if (cur_addr == 0 || phy_addr < cur_addr) { 424 if (cur_addr == 0 || phy_addr < cur_addr) {
425 /* add at front of list - special case with changing head ptr */ 425 /* add at front of list - special case with changing head ptr */
426 if (cur_addr && phy_addr + size > cur_addr) 426 if (cur_addr && phy_addr + size > cur_addr)
427 goto bootmem_free_done; /* error, overlapping section */ 427 goto bootmem_free_done; /* error, overlapping section */
428 else if (phy_addr + size == cur_addr) { 428 else if (phy_addr + size == cur_addr) {
429 /* Add to front of existing first block */ 429 /* Add to front of existing first block */
430 cvmx_bootmem_phy_set_next(phy_addr, 430 cvmx_bootmem_phy_set_next(phy_addr,
@@ -611,7 +611,7 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
611 } 611 }
612 612
613 cvmx_bootmem_unlock(); 613 cvmx_bootmem_unlock();
614 return named_block_ptr != NULL; /* 0 on failure, 1 on success */ 614 return named_block_ptr != NULL; /* 0 on failure, 1 on success */
615} 615}
616 616
617int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, 617int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index fd2015331a20..7c6497781895 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -203,10 +203,10 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
203 * enumeration from the bootloader. 203 * enumeration from the bootloader.
204 * 204 *
205 * @ipd_port: IPD input port associated with the port we want to get link 205 * @ipd_port: IPD input port associated with the port we want to get link
206 * status for. 206 * status for.
207 * 207 *
208 * Returns The ports link status. If the link isn't fully resolved, this must 208 * Returns The ports link status. If the link isn't fully resolved, this must
209 * return zero. 209 * return zero.
210 */ 210 */
211cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) 211cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
212{ 212{
@@ -357,16 +357,16 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
357 result.s.link_up = 1; 357 result.s.link_up = 1;
358 result.s.full_duplex = ((phy_status >> 13) & 1); 358 result.s.full_duplex = ((phy_status >> 13) & 1);
359 switch ((phy_status >> 14) & 3) { 359 switch ((phy_status >> 14) & 3) {
360 case 0: /* 10 Mbps */ 360 case 0: /* 10 Mbps */
361 result.s.speed = 10; 361 result.s.speed = 10;
362 break; 362 break;
363 case 1: /* 100 Mbps */ 363 case 1: /* 100 Mbps */
364 result.s.speed = 100; 364 result.s.speed = 100;
365 break; 365 break;
366 case 2: /* 1 Gbps */ 366 case 2: /* 1 Gbps */
367 result.s.speed = 1000; 367 result.s.speed = 1000;
368 break; 368 break;
369 case 3: /* Illegal */ 369 case 3: /* Illegal */
370 result.u64 = 0; 370 result.u64 = 0;
371 break; 371 break;
372 } 372 }
@@ -391,16 +391,16 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
391 result.s.link_up = inband_status.s.status; 391 result.s.link_up = inband_status.s.status;
392 result.s.full_duplex = inband_status.s.duplex; 392 result.s.full_duplex = inband_status.s.duplex;
393 switch (inband_status.s.speed) { 393 switch (inband_status.s.speed) {
394 case 0: /* 10 Mbps */ 394 case 0: /* 10 Mbps */
395 result.s.speed = 10; 395 result.s.speed = 10;
396 break; 396 break;
397 case 1: /* 100 Mbps */ 397 case 1: /* 100 Mbps */
398 result.s.speed = 100; 398 result.s.speed = 100;
399 break; 399 break;
400 case 2: /* 1 Gbps */ 400 case 2: /* 1 Gbps */
401 result.s.speed = 1000; 401 result.s.speed = 1000;
402 break; 402 break;
403 case 3: /* Illegal */ 403 case 3: /* Illegal */
404 result.u64 = 0; 404 result.u64 = 0;
405 break; 405 break;
406 } 406 }
@@ -429,9 +429,9 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
429 * 429 *
430 * @phy_addr: The address of the PHY to program 430 * @phy_addr: The address of the PHY to program
431 * @enable_autoneg: 431 * @enable_autoneg:
432 * Non zero if you want to enable auto-negotiation. 432 * Non zero if you want to enable auto-negotiation.
433 * @link_info: Link speed to program. If the speed is zero and auto-negotiation 433 * @link_info: Link speed to program. If the speed is zero and auto-negotiation
434 * is enabled, all possible negotiation speeds are advertised. 434 * is enabled, all possible negotiation speeds are advertised.
435 * 435 *
436 * Returns Zero on success, negative on failure 436 * Returns Zero on success, negative on failure
437 */ 437 */
@@ -607,10 +607,10 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
607 * 607 *
608 * @interface: Interface to probe 608 * @interface: Interface to probe
609 * @supported_ports: 609 * @supported_ports:
610 * Number of ports Octeon supports. 610 * Number of ports Octeon supports.
611 * 611 *
612 * Returns Number of ports the actual board supports. Many times this will 612 * Returns Number of ports the actual board supports. Many times this will
613 * simple be "support_ports". 613 * simple be "support_ports".
614 */ 614 */
615int __cvmx_helper_board_interface_probe(int interface, int supported_ports) 615int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
616{ 616{
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
index c1c54890bae0..607b4e659579 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -79,10 +79,10 @@ void cvmx_helper_qlm_jtag_init(void)
79 * @qlm: QLM to shift value into 79 * @qlm: QLM to shift value into
80 * @bits: Number of bits to shift in (1-32). 80 * @bits: Number of bits to shift in (1-32).
81 * @data: Data to shift in. Bit 0 enters the chain first, followed by 81 * @data: Data to shift in. Bit 0 enters the chain first, followed by
82 * bit 1, etc. 82 * bit 1, etc.
83 * 83 *
84 * Returns The low order bits of the JTAG chain that shifted out of the 84 * Returns The low order bits of the JTAG chain that shifted out of the
85 * circle. 85 * circle.
86 */ 86 */
87uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) 87uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
88{ 88{
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
index 82b21843421c..f59c88ee9b31 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -131,7 +131,7 @@ void cvmx_helper_rgmii_internal_loopback(int port)
131 * @interface: Interface to setup 131 * @interface: Interface to setup
132 * @port: Port to setup (0..3) 132 * @port: Port to setup (0..3)
133 * @cpu_clock_hz: 133 * @cpu_clock_hz:
134 * Chip frequency in Hertz 134 * Chip frequency in Hertz
135 * 135 *
136 * Returns Zero on success, negative on failure 136 * Returns Zero on success, negative on failure
137 */ 137 */
@@ -409,14 +409,14 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
409 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); 409 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
410 410
411 /* 411 /*
412 * Port .en .type .p0mii Configuration 412 * Port .en .type .p0mii Configuration
413 * ---- --- ----- ------ ----------------------------------------- 413 * ---- --- ----- ------ -----------------------------------------
414 * X 0 X X All links are disabled. 414 * X 0 X X All links are disabled.
415 * 0 1 X 0 Port 0 is RGMII 415 * 0 1 X 0 Port 0 is RGMII
416 * 0 1 X 1 Port 0 is MII 416 * 0 1 X 1 Port 0 is MII
417 * 1 1 0 X Ports 1 and 2 are configured as RGMII ports. 417 * 1 1 0 X Ports 1 and 2 are configured as RGMII ports.
418 * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or 418 * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or
419 * MII port is selected by GMX_PRT1_CFG[SPEED]. 419 * MII port is selected by GMX_PRT1_CFG[SPEED].
420 */ 420 */
421 421
422 /* In MII mode, CLK_CNT = 1. */ 422 /* In MII mode, CLK_CNT = 1. */
@@ -464,9 +464,9 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
464 * 464 *
465 * @ipd_port: IPD/PKO port to loopback. 465 * @ipd_port: IPD/PKO port to loopback.
466 * @enable_internal: 466 * @enable_internal:
467 * Non zero if you want internal loopback 467 * Non zero if you want internal loopback
468 * @enable_external: 468 * @enable_external:
469 * Non zero if you want external loopback 469 * Non zero if you want external loopback
470 * 470 *
471 * Returns Zero on success, negative on failure. 471 * Returns Zero on success, negative on failure.
472 */ 472 */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 0c0bf5d30e70..45f18cce31a9 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -523,9 +523,9 @@ int __cvmx_helper_sgmii_link_set(int ipd_port,
523 * 523 *
524 * @ipd_port: IPD/PKO port to loopback. 524 * @ipd_port: IPD/PKO port to loopback.
525 * @enable_internal: 525 * @enable_internal:
526 * Non zero if you want internal loopback 526 * Non zero if you want internal loopback
527 * @enable_external: 527 * @enable_external:
528 * Non zero if you want external loopback 528 * Non zero if you want external loopback
529 * 529 *
530 * Returns Zero on success, negative on failure. 530 * Returns Zero on success, negative on failure.
531 */ 531 */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
index 2830e4bdf7f3..1f3030c72d88 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
@@ -160,16 +160,16 @@ cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port)
160 result.s.link_up = inband.s.status; 160 result.s.link_up = inband.s.status;
161 result.s.full_duplex = inband.s.duplex; 161 result.s.full_duplex = inband.s.duplex;
162 switch (inband.s.speed) { 162 switch (inband.s.speed) {
163 case 0: /* 10 Mbps */ 163 case 0: /* 10 Mbps */
164 result.s.speed = 10; 164 result.s.speed = 10;
165 break; 165 break;
166 case 1: /* 100 Mbps */ 166 case 1: /* 100 Mbps */
167 result.s.speed = 100; 167 result.s.speed = 100;
168 break; 168 break;
169 case 2: /* 1 Gbps */ 169 case 2: /* 1 Gbps */
170 result.s.speed = 1000; 170 result.s.speed = 1000;
171 break; 171 break;
172 case 3: /* Illegal */ 172 case 3: /* Illegal */
173 result.s.speed = 0; 173 result.s.speed = 0;
174 result.s.link_up = 0; 174 result.s.link_up = 0;
175 break; 175 break;
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
index dfdfe8bdc9c5..65d2bc9a0bde 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -96,9 +96,9 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
96 uint8_t *end_of_data; 96 uint8_t *end_of_data;
97 97
98 cvmx_dprintf("Packet Length: %u\n", work->len); 98 cvmx_dprintf("Packet Length: %u\n", work->len);
99 cvmx_dprintf(" Input Port: %u\n", work->ipprt); 99 cvmx_dprintf(" Input Port: %u\n", work->ipprt);
100 cvmx_dprintf(" QoS: %u\n", work->qos); 100 cvmx_dprintf(" QoS: %u\n", work->qos);
101 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); 101 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
102 102
103 if (work->word2.s.bufs == 0) { 103 if (work->word2.s.bufs == 0) {
104 union cvmx_ipd_wqe_fpa_queue wqe_pool; 104 union cvmx_ipd_wqe_fpa_queue wqe_pool;
@@ -132,14 +132,14 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
132 while (remaining_bytes) { 132 while (remaining_bytes) {
133 start_of_buffer = 133 start_of_buffer =
134 ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; 134 ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
135 cvmx_dprintf(" Buffer Start:%llx\n", 135 cvmx_dprintf(" Buffer Start:%llx\n",
136 (unsigned long long)start_of_buffer); 136 (unsigned long long)start_of_buffer);
137 cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); 137 cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i);
138 cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); 138 cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back);
139 cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); 139 cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool);
140 cvmx_dprintf(" Buffer Data: %llx\n", 140 cvmx_dprintf(" Buffer Data: %llx\n",
141 (unsigned long long)buffer_ptr.s.addr); 141 (unsigned long long)buffer_ptr.s.addr);
142 cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); 142 cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size);
143 143
144 cvmx_dprintf("\t\t"); 144 cvmx_dprintf("\t\t");
145 data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr); 145 data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
@@ -172,11 +172,11 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
172 * 172 *
173 * @queue: Input queue to setup RED on (0-7) 173 * @queue: Input queue to setup RED on (0-7)
174 * @pass_thresh: 174 * @pass_thresh:
175 * Packets will begin slowly dropping when there are less than 175 * Packets will begin slowly dropping when there are less than
176 * this many packet buffers free in FPA 0. 176 * this many packet buffers free in FPA 0.
177 * @drop_thresh: 177 * @drop_thresh:
178 * All incoming packets will be dropped when there are less 178 * All incoming packets will be dropped when there are less
179 * than this many free packet buffers in FPA 0. 179 * than this many free packet buffers in FPA 0.
180 * Returns Zero on success. Negative on failure 180 * Returns Zero on success. Negative on failure
181 */ 181 */
182int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) 182int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
@@ -207,11 +207,11 @@ int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
207 * Setup Random Early Drop to automatically begin dropping packets. 207 * Setup Random Early Drop to automatically begin dropping packets.
208 * 208 *
209 * @pass_thresh: 209 * @pass_thresh:
210 * Packets will begin slowly dropping when there are less than 210 * Packets will begin slowly dropping when there are less than
211 * this many packet buffers free in FPA 0. 211 * this many packet buffers free in FPA 0.
212 * @drop_thresh: 212 * @drop_thresh:
213 * All incoming packets will be dropped when there are less 213 * All incoming packets will be dropped when there are less
214 * than this many free packet buffers in FPA 0. 214 * than this many free packet buffers in FPA 0.
215 * Returns Zero on success. Negative on failure 215 * Returns Zero on success. Negative on failure
216 */ 216 */
217int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) 217int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index 1723248e987d..7653b7e92197 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -321,9 +321,9 @@ int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
321 * 321 *
322 * @ipd_port: IPD/PKO port to loopback. 322 * @ipd_port: IPD/PKO port to loopback.
323 * @enable_internal: 323 * @enable_internal:
324 * Non zero if you want internal loopback 324 * Non zero if you want internal loopback
325 * @enable_external: 325 * @enable_external:
326 * Non zero if you want external loopback 326 * Non zero if you want external loopback
327 * 327 *
328 * Returns Zero on success, negative on failure. 328 * Returns Zero on success, negative on failure.
329 */ 329 */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index fa4963856353..d63d20dfbfb0 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -111,7 +111,7 @@ int cvmx_helper_ports_on_interface(int interface)
111 * @interface: Interface to probe 111 * @interface: Interface to probe
112 * 112 *
113 * Returns Mode of the interface. Unknown or unsupported interfaces return 113 * Returns Mode of the interface. Unknown or unsupported interfaces return
114 * DISABLED. 114 * DISABLED.
115 */ 115 */
116cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) 116cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
117{ 117{
@@ -187,7 +187,7 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
187 * the defines in executive-config.h. 187 * the defines in executive-config.h.
188 * 188 *
189 * @ipd_port: Port to configure. This follows the IPD numbering, not the 189 * @ipd_port: Port to configure. This follows the IPD numbering, not the
190 * per interface numbering 190 * per interface numbering
191 * 191 *
192 * Returns Zero on success, negative on failure 192 * Returns Zero on success, negative on failure
193 */ 193 */
@@ -591,7 +591,7 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
591 * Function to adjust internal IPD pointer alignments 591 * Function to adjust internal IPD pointer alignments
592 * 592 *
593 * Returns 0 on success 593 * Returns 0 on success
594 * !0 on failure 594 * !0 on failure
595 */ 595 */
596int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) 596int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
597{ 597{
@@ -1068,9 +1068,9 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
1068 * 1068 *
1069 * @ipd_port: IPD/PKO port to loopback. 1069 * @ipd_port: IPD/PKO port to loopback.
1070 * @enable_internal: 1070 * @enable_internal:
1071 * Non zero if you want internal loopback 1071 * Non zero if you want internal loopback
1072 * @enable_external: 1072 * @enable_external:
1073 * Non zero if you want external loopback 1073 * Non zero if you want external loopback
1074 * 1074 *
1075 * Returns Zero on success, negative on failure. 1075 * Returns Zero on success, negative on failure.
1076 */ 1076 */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
index 560e034aa024..fa327ec891cd 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
@@ -85,11 +85,11 @@ void __cvmx_interrupt_gmxx_enable(int interface)
85 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { 85 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
86 if (mode.s.en) { 86 if (mode.s.en) {
87 switch (mode.cn56xx.mode) { 87 switch (mode.cn56xx.mode) {
88 case 1: /* XAUI */ 88 case 1: /* XAUI */
89 num_ports = 1; 89 num_ports = 1;
90 break; 90 break;
91 case 2: /* SGMII */ 91 case 2: /* SGMII */
92 case 3: /* PICMG */ 92 case 3: /* PICMG */
93 num_ports = 4; 93 num_ports = 4;
94 break; 94 break;
95 default: /* Disabled */ 95 default: /* Disabled */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 33b72144db31..42e38c30b540 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -147,7 +147,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
147 mask &= valid_mask; 147 mask &= valid_mask;
148 148
149 /* A UMSK setting which blocks all L2C Ways is an error on some chips */ 149 /* A UMSK setting which blocks all L2C Ways is an error on some chips */
150 if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) 150 if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
151 return -1; 151 return -1;
152 152
153 if (OCTEON_IS_MODEL(OCTEON_CN63XX)) 153 if (OCTEON_IS_MODEL(OCTEON_CN63XX))
@@ -438,7 +438,7 @@ void cvmx_l2c_flush(void)
438 for (set = 0; set < n_set; set++) { 438 for (set = 0; set < n_set; set++) {
439 for (assoc = 0; assoc < n_assoc; assoc++) { 439 for (assoc = 0; assoc < n_assoc; assoc++) {
440 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 440 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
441 (assoc << assoc_shift) | (set << set_shift)); 441 (assoc << assoc_shift) | (set << set_shift));
442 CVMX_CACHE_WBIL2I(address, 0); 442 CVMX_CACHE_WBIL2I(address, 0);
443 } 443 }
444 } 444 }
@@ -573,8 +573,8 @@ union __cvmx_l2c_tag {
573 * @index: Index of the cacheline 573 * @index: Index of the cacheline
574 * 574 *
575 * Returns The Octeon model specific tag structure. This is 575 * Returns The Octeon model specific tag structure. This is
576 * translated by a wrapper function to a generic form that is 576 * translated by a wrapper function to a generic form that is
577 * easier for applications to use. 577 * easier for applications to use.
578 */ 578 */
579static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index) 579static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
580{ 580{
@@ -618,12 +618,12 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
618 ".set push\n\t" 618 ".set push\n\t"
619 ".set mips64\n\t" 619 ".set mips64\n\t"
620 ".set noreorder\n\t" 620 ".set noreorder\n\t"
621 "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */ 621 "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */
622 "ld $0, 0(%[dbg_addr])\n\t" 622 "ld $0, 0(%[dbg_addr])\n\t"
623 "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */ 623 "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */
624 "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */ 624 "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */
625 "ld $0, 0(%[dbg_addr])\n\t" 625 "ld $0, 0(%[dbg_addr])\n\t"
626 "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */ 626 "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */
627 ".set pop" 627 ".set pop"
628 : [tag_val] "=r" (tag_val) 628 : [tag_val] "=r" (tag_val)
629 : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr) 629 : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
@@ -664,10 +664,10 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
664 CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */ 664 CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */
665 l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0)); 665 l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
666 666
667 tag.s.V = l2c_tadx_tag.s.valid; 667 tag.s.V = l2c_tadx_tag.s.valid;
668 tag.s.D = l2c_tadx_tag.s.dirty; 668 tag.s.D = l2c_tadx_tag.s.dirty;
669 tag.s.L = l2c_tadx_tag.s.lock; 669 tag.s.L = l2c_tadx_tag.s.lock;
670 tag.s.U = l2c_tadx_tag.s.use; 670 tag.s.U = l2c_tadx_tag.s.use;
671 tag.s.addr = l2c_tadx_tag.s.tag; 671 tag.s.addr = l2c_tadx_tag.s.tag;
672 } else { 672 } else {
673 union __cvmx_l2c_tag tmp_tag; 673 union __cvmx_l2c_tag tmp_tag;
@@ -679,34 +679,34 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
679 * as it can represent all models. 679 * as it can represent all models.
680 */ 680 */
681 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) { 681 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
682 tag.s.V = tmp_tag.cn58xx.V; 682 tag.s.V = tmp_tag.cn58xx.V;
683 tag.s.D = tmp_tag.cn58xx.D; 683 tag.s.D = tmp_tag.cn58xx.D;
684 tag.s.L = tmp_tag.cn58xx.L; 684 tag.s.L = tmp_tag.cn58xx.L;
685 tag.s.U = tmp_tag.cn58xx.U; 685 tag.s.U = tmp_tag.cn58xx.U;
686 tag.s.addr = tmp_tag.cn58xx.addr; 686 tag.s.addr = tmp_tag.cn58xx.addr;
687 } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { 687 } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
688 tag.s.V = tmp_tag.cn38xx.V; 688 tag.s.V = tmp_tag.cn38xx.V;
689 tag.s.D = tmp_tag.cn38xx.D; 689 tag.s.D = tmp_tag.cn38xx.D;
690 tag.s.L = tmp_tag.cn38xx.L; 690 tag.s.L = tmp_tag.cn38xx.L;
691 tag.s.U = tmp_tag.cn38xx.U; 691 tag.s.U = tmp_tag.cn38xx.U;
692 tag.s.addr = tmp_tag.cn38xx.addr; 692 tag.s.addr = tmp_tag.cn38xx.addr;
693 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { 693 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
694 tag.s.V = tmp_tag.cn31xx.V; 694 tag.s.V = tmp_tag.cn31xx.V;
695 tag.s.D = tmp_tag.cn31xx.D; 695 tag.s.D = tmp_tag.cn31xx.D;
696 tag.s.L = tmp_tag.cn31xx.L; 696 tag.s.L = tmp_tag.cn31xx.L;
697 tag.s.U = tmp_tag.cn31xx.U; 697 tag.s.U = tmp_tag.cn31xx.U;
698 tag.s.addr = tmp_tag.cn31xx.addr; 698 tag.s.addr = tmp_tag.cn31xx.addr;
699 } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { 699 } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
700 tag.s.V = tmp_tag.cn30xx.V; 700 tag.s.V = tmp_tag.cn30xx.V;
701 tag.s.D = tmp_tag.cn30xx.D; 701 tag.s.D = tmp_tag.cn30xx.D;
702 tag.s.L = tmp_tag.cn30xx.L; 702 tag.s.L = tmp_tag.cn30xx.L;
703 tag.s.U = tmp_tag.cn30xx.U; 703 tag.s.U = tmp_tag.cn30xx.U;
704 tag.s.addr = tmp_tag.cn30xx.addr; 704 tag.s.addr = tmp_tag.cn30xx.addr;
705 } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { 705 } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
706 tag.s.V = tmp_tag.cn50xx.V; 706 tag.s.V = tmp_tag.cn50xx.V;
707 tag.s.D = tmp_tag.cn50xx.D; 707 tag.s.D = tmp_tag.cn50xx.D;
708 tag.s.L = tmp_tag.cn50xx.L; 708 tag.s.L = tmp_tag.cn50xx.L;
709 tag.s.U = tmp_tag.cn50xx.U; 709 tag.s.U = tmp_tag.cn50xx.U;
710 tag.s.addr = tmp_tag.cn50xx.addr; 710 tag.s.addr = tmp_tag.cn50xx.addr;
711 } else { 711 } else {
712 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__); 712 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
@@ -865,7 +865,7 @@ void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
865 uint64_t address; 865 uint64_t address;
866 /* Create the address based on index and association. 866 /* Create the address based on index and association.
867 * Bits<20:17> select the way of the cache block involved in 867 * Bits<20:17> select the way of the cache block involved in
868 * the operation 868 * the operation
869 * Bits<16:7> of the effect address select the index 869 * Bits<16:7> of the effect address select the index
870 */ 870 */
871 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 871 address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index f557084b1092..f2c877541597 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -99,7 +99,7 @@ void cvmx_pko_initialize_global(void)
99 * be called after the FPA has been initialized and filled with pages. 99 * be called after the FPA has been initialized and filled with pages.
100 * 100 *
101 * Returns 0 on success 101 * Returns 0 on success
102 * !0 on failure 102 * !0 on failure
103 */ 103 */
104int cvmx_pko_initialize_local(void) 104int cvmx_pko_initialize_local(void)
105{ 105{
@@ -186,19 +186,19 @@ void cvmx_pko_shutdown(void)
186/** 186/**
187 * Configure a output port and the associated queues for use. 187 * Configure a output port and the associated queues for use.
188 * 188 *
189 * @port: Port to configure. 189 * @port: Port to configure.
190 * @base_queue: First queue number to associate with this port. 190 * @base_queue: First queue number to associate with this port.
191 * @num_queues: Number of queues to associate with this port 191 * @num_queues: Number of queues to associate with this port
192 * @priority: Array of priority levels for each queue. Values are 192 * @priority: Array of priority levels for each queue. Values are
193 * allowed to be 0-8. A value of 8 get 8 times the traffic 193 * allowed to be 0-8. A value of 8 get 8 times the traffic
194 * of a value of 1. A value of 0 indicates that no rounds 194 * of a value of 1. A value of 0 indicates that no rounds
195 * will be participated in. These priorities can be changed 195 * will be participated in. These priorities can be changed
196 * on the fly while the pko is enabled. A priority of 9 196 * on the fly while the pko is enabled. A priority of 9
197 * indicates that static priority should be used. If static 197 * indicates that static priority should be used. If static
198 * priority is used all queues with static priority must be 198 * priority is used all queues with static priority must be
199 * contiguous starting at the base_queue, and lower numbered 199 * contiguous starting at the base_queue, and lower numbered
200 * queues have higher priority than higher numbered queues. 200 * queues have higher priority than higher numbered queues.
201 * There must be num_queues elements in the array. 201 * There must be num_queues elements in the array.
202 */ 202 */
203cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, 203cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
204 uint64_t num_queues, 204 uint64_t num_queues,
@@ -440,7 +440,7 @@ void cvmx_pko_show_queue_map()
440 * @port: Port to rate limit 440 * @port: Port to rate limit
441 * @packets_s: Maximum packet/sec 441 * @packets_s: Maximum packet/sec
442 * @burst: Maximum number of packets to burst in a row before rate 442 * @burst: Maximum number of packets to burst in a row before rate
443 * limiting cuts in. 443 * limiting cuts in.
444 * 444 *
445 * Returns Zero on success, negative on failure 445 * Returns Zero on success, negative on failure
446 */ 446 */
@@ -473,7 +473,7 @@ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
473 * @port: Port to rate limit 473 * @port: Port to rate limit
474 * @bits_s: PKO rate limit in bits/sec 474 * @bits_s: PKO rate limit in bits/sec
475 * @burst: Maximum number of bits to burst before rate 475 * @burst: Maximum number of bits to burst before rate
476 * limiting cuts in. 476 * limiting cuts in.
477 * 477 *
478 * Returns Zero on success, negative on failure 478 * Returns Zero on success, negative on failure
479 */ 479 */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index 74afb1710cd9..ef5198d13a0e 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -69,7 +69,7 @@ static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
69/** 69/**
70 * Get current SPI4 initialization callbacks 70 * Get current SPI4 initialization callbacks
71 * 71 *
72 * @callbacks: Pointer to the callbacks structure.to fill 72 * @callbacks: Pointer to the callbacks structure.to fill
73 * 73 *
74 * Returns Pointer to cvmx_spi_callbacks_t structure. 74 * Returns Pointer to cvmx_spi_callbacks_t structure.
75 */ 75 */
@@ -92,11 +92,11 @@ void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks)
92 * Initialize and start the SPI interface. 92 * Initialize and start the SPI interface.
93 * 93 *
94 * @interface: The identifier of the packet interface to configure and 94 * @interface: The identifier of the packet interface to configure and
95 * use as a SPI interface. 95 * use as a SPI interface.
96 * @mode: The operating mode for the SPI interface. The interface 96 * @mode: The operating mode for the SPI interface. The interface
97 * can operate as a full duplex (both Tx and Rx data paths 97 * can operate as a full duplex (both Tx and Rx data paths
98 * active) or as a halfplex (either the Tx data path is 98 * active) or as a halfplex (either the Tx data path is
99 * active or the Rx data path is active, but not both). 99 * active or the Rx data path is active, but not both).
100 * @timeout: Timeout to wait for clock synchronization in seconds 100 * @timeout: Timeout to wait for clock synchronization in seconds
101 * @num_ports: Number of SPI ports to configure 101 * @num_ports: Number of SPI ports to configure
102 * 102 *
@@ -138,11 +138,11 @@ int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout,
138 * with its correspondent system. 138 * with its correspondent system.
139 * 139 *
140 * @interface: The identifier of the packet interface to configure and 140 * @interface: The identifier of the packet interface to configure and
141 * use as a SPI interface. 141 * use as a SPI interface.
142 * @mode: The operating mode for the SPI interface. The interface 142 * @mode: The operating mode for the SPI interface. The interface
143 * can operate as a full duplex (both Tx and Rx data paths 143 * can operate as a full duplex (both Tx and Rx data paths
144 * active) or as a halfplex (either the Tx data path is 144 * active) or as a halfplex (either the Tx data path is
145 * active or the Rx data path is active, but not both). 145 * active or the Rx data path is active, but not both).
146 * @timeout: Timeout to wait for clock synchronization in seconds 146 * @timeout: Timeout to wait for clock synchronization in seconds
147 * 147 *
148 * Returns Zero on success, negative of failure. 148 * Returns Zero on success, negative of failure.
@@ -160,7 +160,7 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
160 INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); 160 INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
161 161
162 /* NOTE: Calendar setup is not performed during restart */ 162 /* NOTE: Calendar setup is not performed during restart */
163 /* Refer to cvmx_spi_start_interface() for the full sequence */ 163 /* Refer to cvmx_spi_start_interface() for the full sequence */
164 164
165 /* Callback to perform clock detection */ 165 /* Callback to perform clock detection */
166 INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); 166 INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
@@ -182,11 +182,11 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
182 * Callback to perform SPI4 reset 182 * Callback to perform SPI4 reset
183 * 183 *
184 * @interface: The identifier of the packet interface to configure and 184 * @interface: The identifier of the packet interface to configure and
185 * use as a SPI interface. 185 * use as a SPI interface.
186 * @mode: The operating mode for the SPI interface. The interface 186 * @mode: The operating mode for the SPI interface. The interface
187 * can operate as a full duplex (both Tx and Rx data paths 187 * can operate as a full duplex (both Tx and Rx data paths
188 * active) or as a halfplex (either the Tx data path is 188 * active) or as a halfplex (either the Tx data path is
189 * active or the Rx data path is active, but not both). 189 * active or the Rx data path is active, but not both).
190 * 190 *
191 * Returns Zero on success, non-zero error code on failure (will cause 191 * Returns Zero on success, non-zero error code on failure (will cause
192 * SPI initialization to abort) 192 * SPI initialization to abort)
@@ -297,11 +297,11 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
297 * Callback to setup calendar and miscellaneous settings before clock detection 297 * Callback to setup calendar and miscellaneous settings before clock detection
298 * 298 *
299 * @interface: The identifier of the packet interface to configure and 299 * @interface: The identifier of the packet interface to configure and
300 * use as a SPI interface. 300 * use as a SPI interface.
301 * @mode: The operating mode for the SPI interface. The interface 301 * @mode: The operating mode for the SPI interface. The interface
302 * can operate as a full duplex (both Tx and Rx data paths 302 * can operate as a full duplex (both Tx and Rx data paths
303 * active) or as a halfplex (either the Tx data path is 303 * active) or as a halfplex (either the Tx data path is
304 * active or the Rx data path is active, but not both). 304 * active or the Rx data path is active, but not both).
305 * @num_ports: Number of ports to configure on SPI 305 * @num_ports: Number of ports to configure on SPI
306 * 306 *
307 * Returns Zero on success, non-zero error code on failure (will cause 307 * Returns Zero on success, non-zero error code on failure (will cause
@@ -382,7 +382,7 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
382 stxx_spi4_dat.u64 = 0; 382 stxx_spi4_dat.u64 = 0;
383 /*Minimum needed by dynamic alignment */ 383 /*Minimum needed by dynamic alignment */
384 stxx_spi4_dat.s.alpha = 32; 384 stxx_spi4_dat.s.alpha = 32;
385 stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */ 385 stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
386 cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), 386 cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
387 stxx_spi4_dat.u64); 387 stxx_spi4_dat.u64);
388 388
@@ -416,11 +416,11 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
416 * Callback to perform clock detection 416 * Callback to perform clock detection
417 * 417 *
418 * @interface: The identifier of the packet interface to configure and 418 * @interface: The identifier of the packet interface to configure and
419 * use as a SPI interface. 419 * use as a SPI interface.
420 * @mode: The operating mode for the SPI interface. The interface 420 * @mode: The operating mode for the SPI interface. The interface
421 * can operate as a full duplex (both Tx and Rx data paths 421 * can operate as a full duplex (both Tx and Rx data paths
422 * active) or as a halfplex (either the Tx data path is 422 * active) or as a halfplex (either the Tx data path is
423 * active or the Rx data path is active, but not both). 423 * active or the Rx data path is active, but not both).
424 * @timeout: Timeout to wait for clock synchronization in seconds 424 * @timeout: Timeout to wait for clock synchronization in seconds
425 * 425 *
426 * Returns Zero on success, non-zero error code on failure (will cause 426 * Returns Zero on success, non-zero error code on failure (will cause
@@ -494,11 +494,11 @@ int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
494 * Callback to perform link training 494 * Callback to perform link training
495 * 495 *
496 * @interface: The identifier of the packet interface to configure and 496 * @interface: The identifier of the packet interface to configure and
497 * use as a SPI interface. 497 * use as a SPI interface.
498 * @mode: The operating mode for the SPI interface. The interface 498 * @mode: The operating mode for the SPI interface. The interface
499 * can operate as a full duplex (both Tx and Rx data paths 499 * can operate as a full duplex (both Tx and Rx data paths
500 * active) or as a halfplex (either the Tx data path is 500 * active) or as a halfplex (either the Tx data path is
501 * active or the Rx data path is active, but not both). 501 * active or the Rx data path is active, but not both).
502 * @timeout: Timeout to wait for link to be trained (in seconds) 502 * @timeout: Timeout to wait for link to be trained (in seconds)
503 * 503 *
504 * Returns Zero on success, non-zero error code on failure (will cause 504 * Returns Zero on success, non-zero error code on failure (will cause
@@ -563,11 +563,11 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
563 * Callback to perform calendar data synchronization 563 * Callback to perform calendar data synchronization
564 * 564 *
565 * @interface: The identifier of the packet interface to configure and 565 * @interface: The identifier of the packet interface to configure and
566 * use as a SPI interface. 566 * use as a SPI interface.
567 * @mode: The operating mode for the SPI interface. The interface 567 * @mode: The operating mode for the SPI interface. The interface
568 * can operate as a full duplex (both Tx and Rx data paths 568 * can operate as a full duplex (both Tx and Rx data paths
569 * active) or as a halfplex (either the Tx data path is 569 * active) or as a halfplex (either the Tx data path is
570 * active or the Rx data path is active, but not both). 570 * active or the Rx data path is active, but not both).
571 * @timeout: Timeout to wait for calendar data in seconds 571 * @timeout: Timeout to wait for calendar data in seconds
572 * 572 *
573 * Returns Zero on success, non-zero error code on failure (will cause 573 * Returns Zero on success, non-zero error code on failure (will cause
@@ -620,11 +620,11 @@ int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
620 * Callback to handle interface up 620 * Callback to handle interface up
621 * 621 *
622 * @interface: The identifier of the packet interface to configure and 622 * @interface: The identifier of the packet interface to configure and
623 * use as a SPI interface. 623 * use as a SPI interface.
624 * @mode: The operating mode for the SPI interface. The interface 624 * @mode: The operating mode for the SPI interface. The interface
625 * can operate as a full duplex (both Tx and Rx data paths 625 * can operate as a full duplex (both Tx and Rx data paths
626 * active) or as a halfplex (either the Tx data path is 626 * active) or as a halfplex (either the Tx data path is
627 * active or the Rx data path is active, but not both). 627 * active or the Rx data path is active, but not both).
628 * 628 *
629 * Returns Zero on success, non-zero error code on failure (will cause 629 * Returns Zero on success, non-zero error code on failure (will cause
630 * SPI initialization to abort) 630 * SPI initialization to abort)
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
index 8b18a20cc7b3..3d17fac29359 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -74,26 +74,26 @@ EXPORT_SYMBOL(cvmx_sysinfo_get);
74 74
75/** 75/**
76 * This function is used in non-simple executive environments (such as 76 * This function is used in non-simple executive environments (such as
77 * Linux kernel, u-boot, etc.) to configure the minimal fields that 77 * Linux kernel, u-boot, etc.) to configure the minimal fields that
78 * are required to use simple executive files directly. 78 * are required to use simple executive files directly.
79 * 79 *
80 * Locking (if required) must be handled outside of this 80 * Locking (if required) must be handled outside of this
81 * function 81 * function
82 * 82 *
83 * @phy_mem_desc_ptr: 83 * @phy_mem_desc_ptr:
84 * Pointer to global physical memory descriptor 84 * Pointer to global physical memory descriptor
85 * (bootmem descriptor) @board_type: Octeon board 85 * (bootmem descriptor) @board_type: Octeon board
86 * type enumeration 86 * type enumeration
87 * 87 *
88 * @board_rev_major: 88 * @board_rev_major:
89 * Board major revision 89 * Board major revision
90 * @board_rev_minor: 90 * @board_rev_minor:
91 * Board minor revision 91 * Board minor revision
92 * @cpu_clock_hz: 92 * @cpu_clock_hz:
93 * CPU clock freqency in hertz 93 * CPU clock freqency in hertz
94 * 94 *
95 * Returns 0: Failure 95 * Returns 0: Failure
96 * 1: success 96 * 1: success
97 */ 97 */
98int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr, 98int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
99 uint16_t board_type, 99 uint16_t board_type,
diff --git a/arch/mips/cavium-octeon/oct_ilm.c b/arch/mips/cavium-octeon/oct_ilm.c
new file mode 100644
index 000000000000..71b213dbb621
--- /dev/null
+++ b/arch/mips/cavium-octeon/oct_ilm.c
@@ -0,0 +1,206 @@
1#include <linux/fs.h>
2#include <linux/interrupt.h>
3#include <asm/octeon/octeon.h>
4#include <asm/octeon/cvmx-ciu-defs.h>
5#include <asm/octeon/cvmx.h>
6#include <linux/debugfs.h>
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/seq_file.h>
10
11#define TIMER_NUM 3
12
13static bool reset_stats;
14
15struct latency_info {
16 u64 io_interval;
17 u64 cpu_interval;
18 u64 timer_start1;
19 u64 timer_start2;
20 u64 max_latency;
21 u64 min_latency;
22 u64 latency_sum;
23 u64 average_latency;
24 u64 interrupt_cnt;
25};
26
27static struct latency_info li;
28static struct dentry *dir;
29
30static int show_latency(struct seq_file *m, void *v)
31{
32 u64 cpuclk, avg, max, min;
33 struct latency_info curr_li = li;
34
35 cpuclk = octeon_get_clock_rate();
36
37 max = (curr_li.max_latency * 1000000000) / cpuclk;
38 min = (curr_li.min_latency * 1000000000) / cpuclk;
39 avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt);
40
41 seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n",
42 curr_li.interrupt_cnt, avg, max, min);
43 return 0;
44}
45
46static int oct_ilm_open(struct inode *inode, struct file *file)
47{
48 return single_open(file, show_latency, NULL);
49}
50
51static const struct file_operations oct_ilm_ops = {
52 .open = oct_ilm_open,
53 .read = seq_read,
54 .llseek = seq_lseek,
55 .release = single_release,
56};
57
58static int reset_statistics(void *data, u64 value)
59{
60 reset_stats = true;
61 return 0;
62}
63
64DEFINE_SIMPLE_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n");
65
66static int init_debufs(void)
67{
68 struct dentry *show_dentry;
69 dir = debugfs_create_dir("oct_ilm", 0);
70 if (!dir) {
71 pr_err("oct_ilm: failed to create debugfs entry oct_ilm\n");
72 return -1;
73 }
74
75 show_dentry = debugfs_create_file("statistics", 0222, dir, NULL,
76 &oct_ilm_ops);
77 if (!show_dentry) {
78 pr_err("oct_ilm: failed to create debugfs entry oct_ilm/statistics\n");
79 return -1;
80 }
81
82 show_dentry = debugfs_create_file("reset", 0222, dir, NULL,
83 &reset_statistics_ops);
84 if (!show_dentry) {
85 pr_err("oct_ilm: failed to create debugfs entry oct_ilm/reset\n");
86 return -1;
87 }
88
89 return 0;
90
91}
92
93static void init_latency_info(struct latency_info *li, int startup)
94{
95 /* interval in milli seconds after which the interrupt will
96 * be triggered
97 */
98 int interval = 1;
99
100 if (startup) {
101 /* Calculating by the amounts io clock and cpu clock would
102 * increment in interval amount of ms
103 */
104 li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000;
105 li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000;
106 }
107 li->timer_start1 = 0;
108 li->timer_start2 = 0;
109 li->max_latency = 0;
110 li->min_latency = (u64)-1;
111 li->latency_sum = 0;
112 li->interrupt_cnt = 0;
113}
114
115
116static void start_timer(int timer, u64 interval)
117{
118 union cvmx_ciu_timx timx;
119 unsigned long flags;
120
121 timx.u64 = 0;
122 timx.s.one_shot = 1;
123 timx.s.len = interval;
124 raw_local_irq_save(flags);
125 li.timer_start1 = read_c0_cvmcount();
126 cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
127 /* Read it back to force wait until register is written. */
128 timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
129 li.timer_start2 = read_c0_cvmcount();
130 raw_local_irq_restore(flags);
131}
132
133
134static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id)
135{
136 u64 last_latency;
137 u64 last_int_cnt;
138
139 if (reset_stats) {
140 init_latency_info(&li, 0);
141 reset_stats = false;
142 } else {
143 last_int_cnt = read_c0_cvmcount();
144 last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval);
145 li.interrupt_cnt++;
146 li.latency_sum += last_latency;
147 if (last_latency > li.max_latency)
148 li.max_latency = last_latency;
149 if (last_latency < li.min_latency)
150 li.min_latency = last_latency;
151 }
152 start_timer(TIMER_NUM, li.io_interval);
153 return IRQ_HANDLED;
154}
155
156static void disable_timer(int timer)
157{
158 union cvmx_ciu_timx timx;
159
160 timx.s.one_shot = 0;
161 timx.s.len = 0;
162 cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
163 /* Read it back to force immediate write of timer register*/
164 timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
165}
166
167static __init int oct_ilm_module_init(void)
168{
169 int rc;
170 int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM;
171
172 rc = init_debufs();
173 if (rc) {
174 WARN(1, "Could not create debugfs entries");
175 return rc;
176 }
177
178 rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD,
179 "oct_ilm", 0);
180 if (rc) {
181 WARN(1, "Could not acquire IRQ %d", irq);
182 goto err_irq;
183 }
184
185 init_latency_info(&li, 1);
186 start_timer(TIMER_NUM, li.io_interval);
187
188 return 0;
189err_irq:
190 debugfs_remove_recursive(dir);
191 return rc;
192}
193
194static __exit void oct_ilm_module_exit(void)
195{
196 disable_timer(TIMER_NUM);
197 if (dir)
198 debugfs_remove_recursive(dir);
199 free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0);
200}
201
202module_exit(oct_ilm_module_exit);
203module_init(oct_ilm_module_init);
204MODULE_AUTHOR("Venkat Subbiah, Cavium");
205MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips.");
206MODULE_LICENSE("GPL");
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 46f5dbceeecc..156aa6143e11 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1542,7 +1542,7 @@ static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1542 1542
1543 if (line == 3) /* MIO */ 1543 if (line == 3) /* MIO */
1544 switch (bit) { 1544 switch (bit) {
1545 case 2: /* IPD_DRP */ 1545 case 2: /* IPD_DRP */
1546 case 8 ... 11: /* Timers */ 1546 case 8 ... 11: /* Timers */
1547 case 48: /* PTP */ 1547 case 48: /* PTP */
1548 edge = true; 1548 edge = true;
@@ -1553,7 +1553,7 @@ static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
1553 else if (line == 6) /* PKT */ 1553 else if (line == 6) /* PKT */
1554 switch (bit) { 1554 switch (bit) {
1555 case 52 ... 53: /* ILK_DRP */ 1555 case 52 ... 53: /* ILK_DRP */
1556 case 8 ... 12: /* GMX_DRP */ 1556 case 8 ... 12: /* GMX_DRP */
1557 edge = true; 1557 edge = true;
1558 break; 1558 break;
1559 default: 1559 default:
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
index 0ba0eb96d9ac..64e08df51d65 100644
--- a/arch/mips/cavium-octeon/octeon-memcpy.S
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -116,15 +116,15 @@
116 116
117#ifdef CONFIG_CPU_LITTLE_ENDIAN 117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define LDFIRST LOADR 118#define LDFIRST LOADR
119#define LDREST LOADL 119#define LDREST LOADL
120#define STFIRST STORER 120#define STFIRST STORER
121#define STREST STOREL 121#define STREST STOREL
122#define SHIFT_DISCARD SLLV 122#define SHIFT_DISCARD SLLV
123#else 123#else
124#define LDFIRST LOADL 124#define LDFIRST LOADL
125#define LDREST LOADR 125#define LDREST LOADR
126#define STFIRST STOREL 126#define STFIRST STOREL
127#define STREST STORER 127#define STREST STORER
128#define SHIFT_DISCARD SRLV 128#define SHIFT_DISCARD SRLV
129#endif 129#endif
130 130
@@ -316,9 +316,9 @@ EXC( STORE t0, -8(dst), s_exc_p1u)
316 316
317src_unaligned: 317src_unaligned:
318#define rem t8 318#define rem t8
319 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter 319 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
320 beqz t0, cleanup_src_unaligned 320 beqz t0, cleanup_src_unaligned
321 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 321 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
3221: 3221:
323/* 323/*
324 * Avoid consecutive LD*'s to the same register since some mips 324 * Avoid consecutive LD*'s to the same register since some mips
@@ -326,13 +326,13 @@ src_unaligned:
326 * It's OK to load FIRST(N+1) before REST(N) because the two addresses 326 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
327 * are to the same unit (unless src is aligned, but it's not). 327 * are to the same unit (unless src is aligned, but it's not).
328 */ 328 */
329EXC( LDFIRST t0, FIRST(0)(src), l_exc) 329EXC( LDFIRST t0, FIRST(0)(src), l_exc)
330EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) 330EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
331 SUB len, len, 4*NBYTES 331 SUB len, len, 4*NBYTES
332EXC( LDREST t0, REST(0)(src), l_exc_copy) 332EXC( LDREST t0, REST(0)(src), l_exc_copy)
333EXC( LDREST t1, REST(1)(src), l_exc_copy) 333EXC( LDREST t1, REST(1)(src), l_exc_copy)
334EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) 334EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
335EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) 335EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
336EXC( LDREST t2, REST(2)(src), l_exc_copy) 336EXC( LDREST t2, REST(2)(src), l_exc_copy)
337EXC( LDREST t3, REST(3)(src), l_exc_copy) 337EXC( LDREST t3, REST(3)(src), l_exc_copy)
338 ADD src, src, 4*NBYTES 338 ADD src, src, 4*NBYTES
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 3c1b625a5859..389512e2abd6 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -410,7 +410,7 @@ int __init octeon_prune_device_tree(void)
410 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); 410 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
411 if (pip_path) { 411 if (pip_path) {
412 int pip = fdt_path_offset(initial_boot_params, pip_path); 412 int pip = fdt_path_offset(initial_boot_params, pip_path);
413 if (pip >= 0) 413 if (pip >= 0)
414 for (i = 0; i <= 4; i++) 414 for (i = 0; i <= 4; i++)
415 octeon_fdt_pip_iface(pip, i, &mac_addr_base); 415 octeon_fdt_pip_iface(pip, i, &mac_addr_base);
416 } 416 }
diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
index f28b2d0fde22..88cb42d4cc49 100644
--- a/arch/mips/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -3,7 +3,7 @@
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. 3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
4 * 4 *
5 * This device tree is pruned and patched by early boot code before 5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available 6 * use. Because of this, it contains a super-set of the available
7 * devices and properties. 7 * devices and properties.
8 */ 8 */
9/ { 9/ {
@@ -433,12 +433,12 @@
433 cavium,t-we = <45>; 433 cavium,t-we = <45>;
434 cavium,t-rd-hld = <35>; 434 cavium,t-rd-hld = <35>;
435 cavium,t-wr-hld = <45>; 435 cavium,t-wr-hld = <45>;
436 cavium,t-pause = <0>; 436 cavium,t-pause = <0>;
437 cavium,t-wait = <0>; 437 cavium,t-wait = <0>;
438 cavium,t-page = <35>; 438 cavium,t-page = <35>;
439 cavium,t-rd-dly = <0>; 439 cavium,t-rd-dly = <0>;
440 440
441 cavium,pages = <0>; 441 cavium,pages = <0>;
442 cavium,bus-width = <8>; 442 cavium,bus-width = <8>;
443 }; 443 };
444 cavium,cs-config@4 { 444 cavium,cs-config@4 {
@@ -450,12 +450,12 @@
450 cavium,t-we = <320>; 450 cavium,t-we = <320>;
451 cavium,t-rd-hld = <320>; 451 cavium,t-rd-hld = <320>;
452 cavium,t-wr-hld = <320>; 452 cavium,t-wr-hld = <320>;
453 cavium,t-pause = <320>; 453 cavium,t-pause = <320>;
454 cavium,t-wait = <320>; 454 cavium,t-wait = <320>;
455 cavium,t-page = <320>; 455 cavium,t-page = <320>;
456 cavium,t-rd-dly = <0>; 456 cavium,t-rd-dly = <0>;
457 457
458 cavium,pages = <0>; 458 cavium,pages = <0>;
459 cavium,bus-width = <8>; 459 cavium,bus-width = <8>;
460 }; 460 };
461 cavium,cs-config@5 { 461 cavium,cs-config@5 {
@@ -467,12 +467,12 @@
467 cavium,t-we = <150>; 467 cavium,t-we = <150>;
468 cavium,t-rd-hld = <100>; 468 cavium,t-rd-hld = <100>;
469 cavium,t-wr-hld = <30>; 469 cavium,t-wr-hld = <30>;
470 cavium,t-pause = <0>; 470 cavium,t-pause = <0>;
471 cavium,t-wait = <30>; 471 cavium,t-wait = <30>;
472 cavium,t-page = <320>; 472 cavium,t-page = <320>;
473 cavium,t-rd-dly = <0>; 473 cavium,t-rd-dly = <0>;
474 474
475 cavium,pages = <0>; 475 cavium,pages = <0>;
476 cavium,bus-width = <16>; 476 cavium,bus-width = <16>;
477 }; 477 };
478 cavium,cs-config@6 { 478 cavium,cs-config@6 {
@@ -484,12 +484,12 @@
484 cavium,t-we = <150>; 484 cavium,t-we = <150>;
485 cavium,t-rd-hld = <100>; 485 cavium,t-rd-hld = <100>;
486 cavium,t-wr-hld = <70>; 486 cavium,t-wr-hld = <70>;
487 cavium,t-pause = <0>; 487 cavium,t-pause = <0>;
488 cavium,t-wait = <0>; 488 cavium,t-wait = <0>;
489 cavium,t-page = <320>; 489 cavium,t-page = <320>;
490 cavium,t-rd-dly = <0>; 490 cavium,t-rd-dly = <0>;
491 491
492 cavium,pages = <0>; 492 cavium,pages = <0>;
493 cavium,wait-mode; 493 cavium,wait-mode;
494 cavium,bus-width = <16>; 494 cavium,bus-width = <16>;
495 }; 495 };
diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts
index 1839468932b6..79b46fcb0a11 100644
--- a/arch/mips/cavium-octeon/octeon_68xx.dts
+++ b/arch/mips/cavium-octeon/octeon_68xx.dts
@@ -3,7 +3,7 @@
3 * OCTEON 68XX device tree skeleton. 3 * OCTEON 68XX device tree skeleton.
4 * 4 *
5 * This device tree is pruned and patched by early boot code before 5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available 6 * use. Because of this, it contains a super-set of the available
7 * devices and properties. 7 * devices and properties.
8 */ 8 */
9/ { 9/ {
@@ -469,12 +469,12 @@
469 cavium,t-we = <35>; 469 cavium,t-we = <35>;
470 cavium,t-rd-hld = <25>; 470 cavium,t-rd-hld = <25>;
471 cavium,t-wr-hld = <35>; 471 cavium,t-wr-hld = <35>;
472 cavium,t-pause = <0>; 472 cavium,t-pause = <0>;
473 cavium,t-wait = <300>; 473 cavium,t-wait = <300>;
474 cavium,t-page = <25>; 474 cavium,t-page = <25>;
475 cavium,t-rd-dly = <0>; 475 cavium,t-rd-dly = <0>;
476 476
477 cavium,pages = <0>; 477 cavium,pages = <0>;
478 cavium,bus-width = <8>; 478 cavium,bus-width = <8>;
479 }; 479 };
480 cavium,cs-config@4 { 480 cavium,cs-config@4 {
@@ -486,12 +486,12 @@
486 cavium,t-we = <320>; 486 cavium,t-we = <320>;
487 cavium,t-rd-hld = <320>; 487 cavium,t-rd-hld = <320>;
488 cavium,t-wr-hld = <320>; 488 cavium,t-wr-hld = <320>;
489 cavium,t-pause = <320>; 489 cavium,t-pause = <320>;
490 cavium,t-wait = <320>; 490 cavium,t-wait = <320>;
491 cavium,t-page = <320>; 491 cavium,t-page = <320>;
492 cavium,t-rd-dly = <0>; 492 cavium,t-rd-dly = <0>;
493 493
494 cavium,pages = <0>; 494 cavium,pages = <0>;
495 cavium,bus-width = <8>; 495 cavium,bus-width = <8>;
496 }; 496 };
497 cavium,cs-config@5 { 497 cavium,cs-config@5 {
@@ -503,12 +503,12 @@
503 cavium,t-we = <150>; 503 cavium,t-we = <150>;
504 cavium,t-rd-hld = <100>; 504 cavium,t-rd-hld = <100>;
505 cavium,t-wr-hld = <300>; 505 cavium,t-wr-hld = <300>;
506 cavium,t-pause = <0>; 506 cavium,t-pause = <0>;
507 cavium,t-wait = <300>; 507 cavium,t-wait = <300>;
508 cavium,t-page = <310>; 508 cavium,t-page = <310>;
509 cavium,t-rd-dly = <0>; 509 cavium,t-rd-dly = <0>;
510 510
511 cavium,pages = <0>; 511 cavium,pages = <0>;
512 cavium,bus-width = <16>; 512 cavium,bus-width = <16>;
513 }; 513 };
514 cavium,cs-config@6 { 514 cavium,cs-config@6 {
@@ -520,12 +520,12 @@
520 cavium,t-we = <150>; 520 cavium,t-we = <150>;
521 cavium,t-rd-hld = <100>; 521 cavium,t-rd-hld = <100>;
522 cavium,t-wr-hld = <30>; 522 cavium,t-wr-hld = <30>;
523 cavium,t-pause = <0>; 523 cavium,t-pause = <0>;
524 cavium,t-wait = <30>; 524 cavium,t-wait = <30>;
525 cavium,t-page = <310>; 525 cavium,t-page = <310>;
526 cavium,t-rd-dly = <0>; 526 cavium,t-rd-dly = <0>;
527 527
528 cavium,pages = <0>; 528 cavium,pages = <0>;
529 cavium,wait-mode; 529 cavium,wait-mode;
530 cavium,bus-width = <16>; 530 cavium,bus-width = <16>;
531 }; 531 };
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 428864b2ba41..7b066bbca86d 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -31,7 +31,7 @@ struct boot_init_vector {
31 uint32_t k0_val; 31 uint32_t k0_val;
32 /* Address of boot info block structure */ 32 /* Address of boot info block structure */
33 uint64_t boot_info_addr; 33 uint64_t boot_info_addr;
34 uint32_t flags; /* flags */ 34 uint32_t flags; /* flags */
35 uint32_t pad; 35 uint32_t pad;
36}; 36};
37 37
@@ -53,20 +53,20 @@ struct linux_app_boot_info {
53 53
54/* If not to copy a lot of bootloader's structures 54/* If not to copy a lot of bootloader's structures
55 here is only offset of requested member */ 55 here is only offset of requested member */
56#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c 56#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c
57 57
58/* hardcoded in bootloader */ 58/* hardcoded in bootloader */
59#define LABI_ADDR_IN_BOOTLOADER 0x700 59#define LABI_ADDR_IN_BOOTLOADER 0x700
60 60
61#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot" 61#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
62 62
63#define LABI_SIGNATURE 0xAABBCC01 63#define LABI_SIGNATURE 0xAABBCC01
64 64
65/* from uboot-headers/octeon_mem_map.h */ 65/* from uboot-headers/octeon_mem_map.h */
66#define EXCEPTION_BASE_INCR (4 * 1024) 66#define EXCEPTION_BASE_INCR (4 * 1024)
67 /* Increment size for exception base addresses (4k minimum) */ 67 /* Increment size for exception base addresses (4k minimum) */
68#define EXCEPTION_BASE_BASE 0 68#define EXCEPTION_BASE_BASE 0
69#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800) 69#define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800)
70#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE) 70#define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE)
71 71
72#endif /* __OCTEON_BOOT_H__ */ 72#endif /* __OCTEON_BOOT_H__ */
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d7e0a09f77c2..c594a3d4f743 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -319,7 +319,7 @@ EXPORT_SYMBOL(octeon_get_io_clock_rate);
319 * exists on most Cavium evaluation boards. If it doesn't exist, then 319 * exists on most Cavium evaluation boards. If it doesn't exist, then
320 * this function doesn't do anything. 320 * this function doesn't do anything.
321 * 321 *
322 * @s: String to write 322 * @s: String to write
323 */ 323 */
324void octeon_write_lcd(const char *s) 324void octeon_write_lcd(const char *s)
325{ 325{
@@ -341,7 +341,7 @@ void octeon_write_lcd(const char *s)
341/** 341/**
342 * Return the console uart passed by the bootloader 342 * Return the console uart passed by the bootloader
343 * 343 *
344 * Returns uart (0 or 1) 344 * Returns uart (0 or 1)
345 */ 345 */
346int octeon_get_boot_uart(void) 346int octeon_get_boot_uart(void)
347{ 347{
@@ -805,7 +805,7 @@ void __init prom_init(void)
805 /* 805 /*
806 * To do: switch parsing to new style, something like: 806 * To do: switch parsing to new style, something like:
807 * parse_crashkernel(arg, sysinfo->system_dram_size, 807 * parse_crashkernel(arg, sysinfo->system_dram_size,
808 * &crashk_size, &crashk_base); 808 * &crashk_size, &crashk_base);
809 */ 809 */
810#endif 810#endif
811 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 811 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
@@ -1013,7 +1013,7 @@ void __init plat_mem_setup(void)
1013} 1013}
1014 1014
1015/* 1015/*
1016 * Emit one character to the boot UART. Exported for use by the 1016 * Emit one character to the boot UART. Exported for use by the
1017 * watchdog timer. 1017 * watchdog timer.
1018 */ 1018 */
1019int prom_putchar(char c) 1019int prom_putchar(char c)
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index ee1fb9f7f517..295137dfdc37 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -55,7 +55,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
55 55
56/** 56/**
57 * Cause the function described by call_data to be executed on the passed 57 * Cause the function described by call_data to be executed on the passed
58 * cpu. When the function has finished, increment the finished field of 58 * cpu. When the function has finished, increment the finished field of
59 * call_data. 59 * call_data.
60 */ 60 */
61void octeon_send_ipi_single(int cpu, unsigned int action) 61void octeon_send_ipi_single(int cpu, unsigned int action)
@@ -126,8 +126,8 @@ static void octeon_smp_setup(void)
126 126
127#ifdef CONFIG_HOTPLUG_CPU 127#ifdef CONFIG_HOTPLUG_CPU
128 /* 128 /*
129 * The possible CPUs are all those present on the chip. We 129 * The possible CPUs are all those present on the chip. We
130 * will assign CPU numbers for possible cores as well. Cores 130 * will assign CPU numbers for possible cores as well. Cores
131 * are always consecutively numberd from 0. 131 * are always consecutively numberd from 0.
132 */ 132 */
133 for (id = 0; id < num_cores && id < NR_CPUS; id++) { 133 for (id = 0; id < num_cores && id < NR_CPUS; id++) {
@@ -332,7 +332,7 @@ extern void kernel_entry(unsigned long arg1, ...);
332 332
333static void start_after_reset(void) 333static void start_after_reset(void)
334{ 334{
335 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 335 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
336} 336}
337 337
338static int octeon_update_boot_vector(unsigned int cpu) 338static int octeon_update_boot_vector(unsigned int cpu)
@@ -401,7 +401,7 @@ static int __cpuinit register_cavium_notifier(void)
401} 401}
402late_initcall(register_cavium_notifier); 402late_initcall(register_cavium_notifier);
403 403
404#endif /* CONFIG_HOTPLUG_CPU */ 404#endif /* CONFIG_HOTPLUG_CPU */
405 405
406struct plat_smp_ops octeon_smp_ops = { 406struct plat_smp_ops octeon_smp_ops = {
407 .send_ipi_single = octeon_send_ipi_single, 407 .send_ipi_single = octeon_send_ipi_single,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 14:16:34 -0500