MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity

Since the locks are used from interrupt context we need the
irqsave/irqrestore versions of the locking functions.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 6 insertions, 4 deletions

diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 384f1842bfb1..0bda5c5db150 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -182,9 +182,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
 static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
 {
         int cpu;
+        unsigned long flags;
         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
 
-        write_lock(&octeon_irq_ciu0_rwlock);
+        write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = cpu_logical_map(cpu);
                 uint64_t en0 =
@@ -200,7 +201,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
          * of them are done.
          */
         cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
-        write_unlock(&octeon_irq_ciu0_rwlock);
+        write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
 
         return 0;
 }
@@ -299,9 +300,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
 static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
 {
         int cpu;
+        unsigned long flags;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
 
-        write_lock(&octeon_irq_ciu1_rwlock);
+        write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = cpu_logical_map(cpu);
                 uint64_t en1 =
@@ -318,7 +320,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *
          * of them are done.
          */
         cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
-        write_unlock(&octeon_irq_ciu1_rwlock);
+        write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
 
         return 0;
 }