diff options
author | David Daney <ddaney@caviumnetworks.com> | 2010-05-19 17:16:31 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-05-21 16:31:22 -0400 |
commit | 1dd5216e80318b4cb25c1785f5d11a6f042f0a3b (patch) | |
tree | f2fe458c71e2258c2034e6daf9ceb3b330d51334 /arch/mips/cavium-octeon | |
parent | 142a2ceea793b4d134757c226daeb4101d649df0 (diff) |
MIPS: Octeon: Get rid of early serial.
Get rid of early_serial_setup, we use CONFIG_EARLY_PRINTK instead.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1254/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon')
-rw-r--r-- | arch/mips/cavium-octeon/setup.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 9a06fa9f9f0c..44cb20cd3bdc 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c | |||
@@ -403,7 +403,6 @@ void __init prom_init(void) | |||
403 | const int coreid = cvmx_get_core_num(); | 403 | const int coreid = cvmx_get_core_num(); |
404 | int i; | 404 | int i; |
405 | int argc; | 405 | int argc; |
406 | struct uart_port octeon_port; | ||
407 | #ifdef CONFIG_CAVIUM_RESERVE32 | 406 | #ifdef CONFIG_CAVIUM_RESERVE32 |
408 | int64_t addr = -1; | 407 | int64_t addr = -1; |
409 | #endif | 408 | #endif |
@@ -610,30 +609,6 @@ void __init prom_init(void) | |||
610 | _machine_restart = octeon_restart; | 609 | _machine_restart = octeon_restart; |
611 | _machine_halt = octeon_halt; | 610 | _machine_halt = octeon_halt; |
612 | 611 | ||
613 | memset(&octeon_port, 0, sizeof(octeon_port)); | ||
614 | /* | ||
615 | * For early_serial_setup we don't set the port type or | ||
616 | * UPF_FIXED_TYPE. | ||
617 | */ | ||
618 | octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ; | ||
619 | octeon_port.iotype = UPIO_MEM; | ||
620 | /* I/O addresses are every 8 bytes */ | ||
621 | octeon_port.regshift = 3; | ||
622 | /* Clock rate of the chip */ | ||
623 | octeon_port.uartclk = mips_hpt_frequency; | ||
624 | octeon_port.fifosize = 64; | ||
625 | octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart); | ||
626 | octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase); | ||
627 | octeon_port.serial_in = octeon_serial_in; | ||
628 | octeon_port.serial_out = octeon_serial_out; | ||
629 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | ||
630 | octeon_port.line = 0; | ||
631 | #else | ||
632 | octeon_port.line = octeon_uart; | ||
633 | #endif | ||
634 | octeon_port.irq = 42 + octeon_uart; | ||
635 | early_serial_setup(&octeon_port); | ||
636 | |||
637 | octeon_user_io_init(); | 612 | octeon_user_io_init(); |
638 | register_smp_ops(&octeon_smp_ops); | 613 | register_smp_ops(&octeon_smp_ops); |
639 | } | 614 | } |