Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS:

   - a number of fixes that didn't make the 3.19 release.

   - a number of cleanups.

   - preliminary support for Cavium's Octeon 3 SOCs which feature up to
     48 MIPS64 R3 cores with FPU and hardware virtualization.

   - support for MIPS R6 processors.

     Revision 6 of the MIPS architecture is a major revision of the MIPS
     architecture which does away with many of original sins of the
     architecture such as branch delay slots.  This and other changes in
     R6 require major changes throughout the entire MIPS core
     architecture code and make up for the lion share of this pull
     request.

   - finally some preparatory work for eXtendend Physical Address
     support, which allows support of up to 40 bit of physical address
     space on 32 bit processors"

     [ Ahh, MIPS can't leave the PAE brain damage alone.  It's like
       every CPU architect has to make that mistake, but pee in the snow
       by changing the TLA.  But whether it's called PAE, LPAE or XPA,
       it's horrid crud   - Linus ]

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits)
  MIPS: sead3: Corrected get_c0_perfcount_int
  MIPS: mm: Remove dead macro definitions
  MIPS: OCTEON: irq: add CIB and other fixes
  MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.
  MIPS: OCTEON: More OCTEONIII support
  MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.
  MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.
  MIPS: OCTEON: Update octeon-model.h code for new SoCs.
  MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX
  MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h
  MIPS: OCTEON: Implement the core-16057 workaround
  MIPS: OCTEON: Delete unused COP2 saving code
  MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
  MIPS: OCTEON: Save and restore CP2 SHA3 state
  MIPS: OCTEON: Fix FP context save.
  MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs
  MIPS: boot: Provide more uImage options
  MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h
  MIPS: ip22-gio: Remove legacy suspend/resume support
  mips: pci: Add ifdef around pci_proc_domain
  ...

1 files changed, 49 insertions, 7 deletions

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 94f888d3384e..a42110e7edbc 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -41,6 +41,7 @@
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/pci-octeon.h>
 #include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-rst-defs.h>
 
 extern struct plat_smp_ops octeon_smp_ops;
 
@@ -579,12 +580,10 @@ void octeon_user_io_init(void)
         /* R/W If set, CVMSEG is available for loads/stores in user
          * mode. */
         cvmmemctl.s.cvmsegenau = 0;
-        /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
-         * is max legal value. */
-        cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
 
         write_c0_cvmmemctl(cvmmemctl.u64);
 
+        /* Setup of CVMSEG is done in kernel-entry-init.h */
         if (smp_processor_id() == 0)
                 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
@@ -615,6 +614,7 @@ void __init prom_init(void)
         const char *arg;
         char *p;
         int i;
+        u64 t;
         int argc;
 #ifdef CONFIG_CAVIUM_RESERVE32
         int64_t addr = -1;
@@ -654,15 +654,56 @@ void __init prom_init(void)
         sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
         sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
 
-        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+        if (OCTEON_IS_OCTEON2()) {
                 /* I/O clock runs at a different rate than the CPU. */
                 union cvmx_mio_rst_boot rst_boot;
                 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
                 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
+        } else if (OCTEON_IS_OCTEON3()) {
+                /* I/O clock runs at a different rate than the CPU. */
+                union cvmx_rst_boot rst_boot;
+                rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
+                octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
         } else {
                 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
         }
 
+        t = read_c0_cvmctl();
+        if ((t & (1ull << 27)) == 0) {
+                /*
+                 * Setup the multiplier save/restore code if
+                 * CvmCtl[NOMUL] clear.
+                 */
+                void *save;
+                void *save_end;
+                void *restore;
+                void *restore_end;
+                int save_len;
+                int restore_len;
+                int save_max = (char *)octeon_mult_save_end -
+                        (char *)octeon_mult_save;
+                int restore_max = (char *)octeon_mult_restore_end -
+                        (char *)octeon_mult_restore;
+                if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
+                        save = octeon_mult_save3;
+                        save_end = octeon_mult_save3_end;
+                        restore = octeon_mult_restore3;
+                        restore_end = octeon_mult_restore3_end;
+                } else {
+                        save = octeon_mult_save2;
+                        save_end = octeon_mult_save2_end;
+                        restore = octeon_mult_restore2;
+                        restore_end = octeon_mult_restore2_end;
+                }
+                save_len = (char *)save_end - (char *)save;
+                restore_len = (char *)restore_end - (char *)restore;
+                if (!WARN_ON(save_len > save_max ||
+                                restore_len > restore_max)) {
+                        memcpy(octeon_mult_save, save, save_len);
+                        memcpy(octeon_mult_restore, restore, restore_len);
+                }
+        }
+
         /*
          * Only enable the LED controller if we're running on a CN38XX, CN58XX,
          * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
@@ -1004,7 +1045,7 @@ EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
-        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
+        if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
                 /* Check for presence of Core-14449 fix.  */
                 u32 insn;
                 u32 *foo;
@@ -1026,8 +1067,9 @@ void prom_free_prom_memory(void)
                         panic("No PREF instruction at Core-14449 probe point.");
 
                 if (((insn >> 16) & 0x1f) != 28)
-                        panic("Core-14449 WAR not in place (%04x).\n"
-                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
+                        panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
+                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
+                              insn);
         }
 }