diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-06-12 19:29:24 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-06-18 10:28:16 -0400 |
commit | 39205750efa6d335fac4f9bcd32b49c7e71c12b7 (patch) | |
tree | 1005dcd9ce98f83ae3df8ddf12bb28a322a06f1b /arch/mips/cavium-octeon/setup.c | |
parent | c8d5c685647f7ce73ed642a9130e930ab69178d4 (diff) |
MIPS: Oceton: Fix build error.
If CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB, CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION,
CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT and
CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT are all undefined:
arch/mips/cavium-octeon/setup.c: In function ‘prom_init’:
arch/mips/cavium-octeon/setup.c:715:12: error: unused variable ‘ebase’ [-Werror=unused-variable]
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/setup.c')
-rw-r--r-- | arch/mips/cavium-octeon/setup.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 01b1b3f94feb..1bcc144da287 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c | |||
@@ -7,6 +7,7 @@ | |||
7 | * Copyright (C) 2008, 2009 Wind River Systems | 7 | * Copyright (C) 2008, 2009 Wind River Systems |
8 | * written by Ralf Baechle <ralf@linux-mips.org> | 8 | * written by Ralf Baechle <ralf@linux-mips.org> |
9 | */ | 9 | */ |
10 | #include <linux/compiler.h> | ||
10 | #include <linux/init.h> | 11 | #include <linux/init.h> |
11 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
12 | #include <linux/console.h> | 13 | #include <linux/console.h> |
@@ -712,7 +713,7 @@ void __init prom_init(void) | |||
712 | if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { | 713 | if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { |
713 | pr_info("Skipping L2 locking due to reduced L2 cache size\n"); | 714 | pr_info("Skipping L2 locking due to reduced L2 cache size\n"); |
714 | } else { | 715 | } else { |
715 | uint32_t ebase = read_c0_ebase() & 0x3ffff000; | 716 | uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; |
716 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB | 717 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB |
717 | /* TLB refill */ | 718 | /* TLB refill */ |
718 | cvmx_l2c_lock_mem_region(ebase, 0x100); | 719 | cvmx_l2c_lock_mem_region(ebase, 0x100); |