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authorDavid Daney <ddaney@caviumnetworks.com>2009-04-23 20:44:38 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-06-17 06:06:25 -0400
commite8635b484f644c7873e6091f15330c49396f2cbc (patch)
treea12d2a4f22cd29d7b88c4df251eced3b43ea47a7 /arch/mips/cavium-octeon/pcie.c
parent8860fb8210b06720d5fe3c23b2803a211c26feb1 (diff)
MIPS: Add Cavium OCTEON PCI support.
This patch adds support for PCI and PCIe to the base Cavium OCTEON processor support. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/pcie.c')
-rw-r--r--arch/mips/cavium-octeon/pcie.c1370
1 files changed, 1370 insertions, 0 deletions
diff --git a/arch/mips/cavium-octeon/pcie.c b/arch/mips/cavium-octeon/pcie.c
new file mode 100644
index 000000000000..49d14081b3b5
--- /dev/null
+++ b/arch/mips/cavium-octeon/pcie.c
@@ -0,0 +1,1370 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h>
21
22#include "pci-common.h"
23
24union cvmx_pcie_address {
25 uint64_t u64;
26 struct {
27 uint64_t upper:2; /* Normally 2 for XKPHYS */
28 uint64_t reserved_49_61:13; /* Must be zero */
29 uint64_t io:1; /* 1 for IO space access */
30 uint64_t did:5; /* PCIe DID = 3 */
31 uint64_t subdid:3; /* PCIe SubDID = 1 */
32 uint64_t reserved_36_39:4; /* Must be zero */
33 uint64_t es:2; /* Endian swap = 1 */
34 uint64_t port:2; /* PCIe port 0,1 */
35 uint64_t reserved_29_31:3; /* Must be zero */
36 /*
37 * Selects the type of the configuration request (0 = type 0,
38 * 1 = type 1).
39 */
40 uint64_t ty:1;
41 /* Target bus number sent in the ID in the request. */
42 uint64_t bus:8;
43 /*
44 * Target device number sent in the ID in the
45 * request. Note that Dev must be zero for type 0
46 * configuration requests.
47 */
48 uint64_t dev:5;
49 /* Target function number sent in the ID in the request. */
50 uint64_t func:3;
51 /*
52 * Selects a register in the configuration space of
53 * the target.
54 */
55 uint64_t reg:12;
56 } config;
57 struct {
58 uint64_t upper:2; /* Normally 2 for XKPHYS */
59 uint64_t reserved_49_61:13; /* Must be zero */
60 uint64_t io:1; /* 1 for IO space access */
61 uint64_t did:5; /* PCIe DID = 3 */
62 uint64_t subdid:3; /* PCIe SubDID = 2 */
63 uint64_t reserved_36_39:4; /* Must be zero */
64 uint64_t es:2; /* Endian swap = 1 */
65 uint64_t port:2; /* PCIe port 0,1 */
66 uint64_t address:32; /* PCIe IO address */
67 } io;
68 struct {
69 uint64_t upper:2; /* Normally 2 for XKPHYS */
70 uint64_t reserved_49_61:13; /* Must be zero */
71 uint64_t io:1; /* 1 for IO space access */
72 uint64_t did:5; /* PCIe DID = 3 */
73 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
74 uint64_t reserved_36_39:4; /* Must be zero */
75 uint64_t address:36; /* PCIe Mem address */
76 } mem;
77};
78
79/**
80 * Return the Core virtual base address for PCIe IO access. IOs are
81 * read/written as an offset from this address.
82 *
83 * @pcie_port: PCIe port the IO is for
84 *
85 * Returns 64bit Octeon IO base address for read/write
86 */
87static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
88{
89 union cvmx_pcie_address pcie_addr;
90 pcie_addr.u64 = 0;
91 pcie_addr.io.upper = 0;
92 pcie_addr.io.io = 1;
93 pcie_addr.io.did = 3;
94 pcie_addr.io.subdid = 2;
95 pcie_addr.io.es = 1;
96 pcie_addr.io.port = pcie_port;
97 return pcie_addr.u64;
98}
99
100/**
101 * Size of the IO address region returned at address
102 * cvmx_pcie_get_io_base_address()
103 *
104 * @pcie_port: PCIe port the IO is for
105 *
106 * Returns Size of the IO window
107 */
108static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
109{
110 return 1ull << 32;
111}
112
113/**
114 * Return the Core virtual base address for PCIe MEM access. Memory is
115 * read/written as an offset from this address.
116 *
117 * @pcie_port: PCIe port the IO is for
118 *
119 * Returns 64bit Octeon IO base address for read/write
120 */
121static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
122{
123 union cvmx_pcie_address pcie_addr;
124 pcie_addr.u64 = 0;
125 pcie_addr.mem.upper = 0;
126 pcie_addr.mem.io = 1;
127 pcie_addr.mem.did = 3;
128 pcie_addr.mem.subdid = 3 + pcie_port;
129 return pcie_addr.u64;
130}
131
132/**
133 * Size of the Mem address region returned at address
134 * cvmx_pcie_get_mem_base_address()
135 *
136 * @pcie_port: PCIe port the IO is for
137 *
138 * Returns Size of the Mem window
139 */
140static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
141{
142 return 1ull << 36;
143}
144
145/**
146 * Read a PCIe config space register indirectly. This is used for
147 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
148 *
149 * @pcie_port: PCIe port to read from
150 * @cfg_offset: Address to read
151 *
152 * Returns Value read
153 */
154static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
155{
156 union cvmx_pescx_cfg_rd pescx_cfg_rd;
157 pescx_cfg_rd.u64 = 0;
158 pescx_cfg_rd.s.addr = cfg_offset;
159 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
160 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
161 return pescx_cfg_rd.s.data;
162}
163
164/**
165 * Write a PCIe config space register indirectly. This is used for
166 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
167 *
168 * @pcie_port: PCIe port to write to
169 * @cfg_offset: Address to write
170 * @val: Value to write
171 */
172static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
173 uint32_t val)
174{
175 union cvmx_pescx_cfg_wr pescx_cfg_wr;
176 pescx_cfg_wr.u64 = 0;
177 pescx_cfg_wr.s.addr = cfg_offset;
178 pescx_cfg_wr.s.data = val;
179 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
180}
181
182/**
183 * Build a PCIe config space request address for a device
184 *
185 * @pcie_port: PCIe port to access
186 * @bus: Sub bus
187 * @dev: Device ID
188 * @fn: Device sub function
189 * @reg: Register to access
190 *
191 * Returns 64bit Octeon IO address
192 */
193static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
194 int dev, int fn, int reg)
195{
196 union cvmx_pcie_address pcie_addr;
197 union cvmx_pciercx_cfg006 pciercx_cfg006;
198
199 pciercx_cfg006.u32 =
200 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
201 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
202 return 0;
203
204 pcie_addr.u64 = 0;
205 pcie_addr.config.upper = 2;
206 pcie_addr.config.io = 1;
207 pcie_addr.config.did = 3;
208 pcie_addr.config.subdid = 1;
209 pcie_addr.config.es = 1;
210 pcie_addr.config.port = pcie_port;
211 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
212 pcie_addr.config.bus = bus;
213 pcie_addr.config.dev = dev;
214 pcie_addr.config.func = fn;
215 pcie_addr.config.reg = reg;
216 return pcie_addr.u64;
217}
218
219/**
220 * Read 8bits from a Device's config space
221 *
222 * @pcie_port: PCIe port the device is on
223 * @bus: Sub bus
224 * @dev: Device ID
225 * @fn: Device sub function
226 * @reg: Register to access
227 *
228 * Returns Result of the read
229 */
230static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
231 int fn, int reg)
232{
233 uint64_t address =
234 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
235 if (address)
236 return cvmx_read64_uint8(address);
237 else
238 return 0xff;
239}
240
241/**
242 * Read 16bits from a Device's config space
243 *
244 * @pcie_port: PCIe port the device is on
245 * @bus: Sub bus
246 * @dev: Device ID
247 * @fn: Device sub function
248 * @reg: Register to access
249 *
250 * Returns Result of the read
251 */
252static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
253 int fn, int reg)
254{
255 uint64_t address =
256 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
257 if (address)
258 return le16_to_cpu(cvmx_read64_uint16(address));
259 else
260 return 0xffff;
261}
262
263/**
264 * Read 32bits from a Device's config space
265 *
266 * @pcie_port: PCIe port the device is on
267 * @bus: Sub bus
268 * @dev: Device ID
269 * @fn: Device sub function
270 * @reg: Register to access
271 *
272 * Returns Result of the read
273 */
274static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
275 int fn, int reg)
276{
277 uint64_t address =
278 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
279 if (address)
280 return le32_to_cpu(cvmx_read64_uint32(address));
281 else
282 return 0xffffffff;
283}
284
285/**
286 * Write 8bits to a Device's config space
287 *
288 * @pcie_port: PCIe port the device is on
289 * @bus: Sub bus
290 * @dev: Device ID
291 * @fn: Device sub function
292 * @reg: Register to access
293 * @val: Value to write
294 */
295static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
296 int reg, uint8_t val)
297{
298 uint64_t address =
299 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
300 if (address)
301 cvmx_write64_uint8(address, val);
302}
303
304/**
305 * Write 16bits to a Device's config space
306 *
307 * @pcie_port: PCIe port the device is on
308 * @bus: Sub bus
309 * @dev: Device ID
310 * @fn: Device sub function
311 * @reg: Register to access
312 * @val: Value to write
313 */
314static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
315 int reg, uint16_t val)
316{
317 uint64_t address =
318 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
319 if (address)
320 cvmx_write64_uint16(address, cpu_to_le16(val));
321}
322
323/**
324 * Write 32bits to a Device's config space
325 *
326 * @pcie_port: PCIe port the device is on
327 * @bus: Sub bus
328 * @dev: Device ID
329 * @fn: Device sub function
330 * @reg: Register to access
331 * @val: Value to write
332 */
333static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
334 int reg, uint32_t val)
335{
336 uint64_t address =
337 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
338 if (address)
339 cvmx_write64_uint32(address, cpu_to_le32(val));
340}
341
342/**
343 * Initialize the RC config space CSRs
344 *
345 * @pcie_port: PCIe port to initialize
346 */
347static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
348{
349 union cvmx_pciercx_cfg030 pciercx_cfg030;
350 union cvmx_npei_ctl_status2 npei_ctl_status2;
351 union cvmx_pciercx_cfg070 pciercx_cfg070;
352 union cvmx_pciercx_cfg001 pciercx_cfg001;
353 union cvmx_pciercx_cfg032 pciercx_cfg032;
354 union cvmx_pciercx_cfg006 pciercx_cfg006;
355 union cvmx_pciercx_cfg008 pciercx_cfg008;
356 union cvmx_pciercx_cfg009 pciercx_cfg009;
357 union cvmx_pciercx_cfg010 pciercx_cfg010;
358 union cvmx_pciercx_cfg011 pciercx_cfg011;
359 union cvmx_pciercx_cfg035 pciercx_cfg035;
360 union cvmx_pciercx_cfg075 pciercx_cfg075;
361 union cvmx_pciercx_cfg034 pciercx_cfg034;
362
363 /* Max Payload Size (PCIE*_CFG030[MPS]) */
364 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
365 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
366 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
367 pciercx_cfg030.u32 =
368 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
369 /*
370 * Max payload size = 128 bytes for best Octeon DMA
371 * performance.
372 */
373 pciercx_cfg030.s.mps = 0;
374 /*
375 * Max read request size = 128 bytes for best Octeon DMA
376 * performance.
377 */
378 pciercx_cfg030.s.mrrs = 0;
379 /* Enable relaxed ordering. */
380 pciercx_cfg030.s.ro_en = 1;
381 /* Enable no snoop. */
382 pciercx_cfg030.s.ns_en = 1;
383 /* Correctable error reporting enable. */
384 pciercx_cfg030.s.ce_en = 1;
385 /* Non-fatal error reporting enable. */
386 pciercx_cfg030.s.nfe_en = 1;
387 /* Fatal error reporting enable. */
388 pciercx_cfg030.s.fe_en = 1;
389 /* Unsupported request reporting enable. */
390 pciercx_cfg030.s.ur_en = 1;
391 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
392 pciercx_cfg030.u32);
393
394 /*
395 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
396 * PCIE*_CFG030[MPS]
397 *
398 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
399 * exceed PCIE*_CFG030[MRRS].
400 */
401 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
402 /* Max payload size = 128 bytes for best Octeon DMA performance */
403 npei_ctl_status2.s.mps = 0;
404 /* Max read request size = 128 bytes for best Octeon DMA performance */
405 npei_ctl_status2.s.mrrs = 0;
406 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
407
408 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
409 pciercx_cfg070.u32 =
410 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
411 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
412 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
413 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
414 pciercx_cfg070.u32);
415
416 /*
417 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
418 * always be set.
419 *
420 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
421 * Message Enable (PCIE*_CFG001[SEE])
422 */
423 pciercx_cfg001.u32 =
424 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
425 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
426 pciercx_cfg001.s.me = 1; /* Bus master enable. */
427 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
428 pciercx_cfg001.s.see = 1; /* SERR# enable */
429 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
430 pciercx_cfg001.u32);
431
432 /* Advanced Error Recovery Message Enables */
433 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
434 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
435 /* Use CVMX_PCIERCX_CFG067 hardware default */
436 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
437
438 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
439 pciercx_cfg032.u32 =
440 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
441 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
442 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
443 pciercx_cfg032.u32);
444
445 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
446
447 /*
448 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
449 * cvmx_pcie_rc_initialize_link()
450 *
451 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
452 *
453 * We set the primary bus number to 1 so IDT bridges are
454 * happy. They don't like zero.
455 */
456 pciercx_cfg006.u32 = 0;
457 pciercx_cfg006.s.pbnum = 1;
458 pciercx_cfg006.s.sbnum = 1;
459 pciercx_cfg006.s.subbnum = 1;
460 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
461 pciercx_cfg006.u32);
462
463 /*
464 * Memory-mapped I/O BAR (PCIERCn_CFG008)
465 * Most applications should disable the memory-mapped I/O BAR by
466 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
467 */
468 pciercx_cfg008.u32 = 0;
469 pciercx_cfg008.s.mb_addr = 0x100;
470 pciercx_cfg008.s.ml_addr = 0;
471 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
472 pciercx_cfg008.u32);
473
474 /*
475 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
476 * Most applications should disable the prefetchable BAR by setting
477 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
478 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
479 */
480 pciercx_cfg009.u32 =
481 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
482 pciercx_cfg010.u32 =
483 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
484 pciercx_cfg011.u32 =
485 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
486 pciercx_cfg009.s.lmem_base = 0x100;
487 pciercx_cfg009.s.lmem_limit = 0;
488 pciercx_cfg010.s.umem_base = 0x100;
489 pciercx_cfg011.s.umem_limit = 0;
490 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
491 pciercx_cfg009.u32);
492 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
493 pciercx_cfg010.u32);
494 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
495 pciercx_cfg011.u32);
496
497 /*
498 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
499 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
500 */
501 pciercx_cfg035.u32 =
502 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
503 /* System error on correctable error enable. */
504 pciercx_cfg035.s.secee = 1;
505 /* System error on fatal error enable. */
506 pciercx_cfg035.s.sefee = 1;
507 /* System error on non-fatal error enable. */
508 pciercx_cfg035.s.senfee = 1;
509 /* PME interrupt enable. */
510 pciercx_cfg035.s.pmeie = 1;
511 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
512 pciercx_cfg035.u32);
513
514 /*
515 * Advanced Error Recovery Interrupt Enables
516 * (PCIERCn_CFG075[CERE,NFERE,FERE])
517 */
518 pciercx_cfg075.u32 =
519 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
520 /* Correctable error reporting enable. */
521 pciercx_cfg075.s.cere = 1;
522 /* Non-fatal error reporting enable. */
523 pciercx_cfg075.s.nfere = 1;
524 /* Fatal error reporting enable. */
525 pciercx_cfg075.s.fere = 1;
526 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
527 pciercx_cfg075.u32);
528
529 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
530 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
531 */
532 pciercx_cfg034.u32 =
533 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
534 /* Hot-plug interrupt enable. */
535 pciercx_cfg034.s.hpint_en = 1;
536 /* Data Link Layer state changed enable */
537 pciercx_cfg034.s.dlls_en = 1;
538 /* Command completed interrupt enable. */
539 pciercx_cfg034.s.ccint_en = 1;
540 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
541 pciercx_cfg034.u32);
542}
543
544/**
545 * Initialize a host mode PCIe link. This function takes a PCIe
546 * port from reset to a link up state. Software can then begin
547 * configuring the rest of the link.
548 *
549 * @pcie_port: PCIe port to initialize
550 *
551 * Returns Zero on success
552 */
553static int __cvmx_pcie_rc_initialize_link(int pcie_port)
554{
555 uint64_t start_cycle;
556 union cvmx_pescx_ctl_status pescx_ctl_status;
557 union cvmx_pciercx_cfg452 pciercx_cfg452;
558 union cvmx_pciercx_cfg032 pciercx_cfg032;
559 union cvmx_pciercx_cfg448 pciercx_cfg448;
560
561 /* Set the lane width */
562 pciercx_cfg452.u32 =
563 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
564 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
565 if (pescx_ctl_status.s.qlm_cfg == 0) {
566 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
567 pciercx_cfg452.s.lme = 0xf;
568 } else {
569 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
570 pciercx_cfg452.s.lme = 0x7;
571 }
572 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
573 pciercx_cfg452.u32);
574
575 /*
576 * CN52XX pass 1.x has an errata where length mismatches on UR
577 * responses can cause bus errors on 64bit memory
578 * reads. Turning off length error checking fixes this.
579 */
580 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
581 union cvmx_pciercx_cfg455 pciercx_cfg455;
582 pciercx_cfg455.u32 =
583 cvmx_pcie_cfgx_read(pcie_port,
584 CVMX_PCIERCX_CFG455(pcie_port));
585 pciercx_cfg455.s.m_cpl_len_err = 1;
586 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
587 pciercx_cfg455.u32);
588 }
589
590 /* Lane swap needs to be manually enabled for CN52XX */
591 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
592 pescx_ctl_status.s.lane_swp = 1;
593 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
594 pescx_ctl_status.u64);
595 }
596
597 /* Bring up the link */
598 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
599 pescx_ctl_status.s.lnk_enb = 1;
600 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
601
602 /*
603 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
604 * be disabled.
605 */
606 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
607 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
608
609 /* Wait for the link to come up */
610 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
611 start_cycle = cvmx_get_cycle();
612 do {
613 if (cvmx_get_cycle() - start_cycle >
614 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
615 cvmx_dprintf("PCIe: Port %d link timeout\n",
616 pcie_port);
617 return -1;
618 }
619 cvmx_wait(10000);
620 pciercx_cfg032.u32 =
621 cvmx_pcie_cfgx_read(pcie_port,
622 CVMX_PCIERCX_CFG032(pcie_port));
623 } while (pciercx_cfg032.s.dlla == 0);
624
625 /* Display the link status */
626 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
627 pciercx_cfg032.s.nlw);
628
629 /*
630 * Update the Replay Time Limit. Empirically, some PCIe
631 * devices take a little longer to respond than expected under
632 * load. As a workaround for this we configure the Replay Time
633 * Limit to the value expected for a 512 byte MPS instead of
634 * our actual 256 byte MPS. The numbers below are directly
635 * from the PCIe spec table 3-4.
636 */
637 pciercx_cfg448.u32 =
638 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
639 switch (pciercx_cfg032.s.nlw) {
640 case 1: /* 1 lane */
641 pciercx_cfg448.s.rtl = 1677;
642 break;
643 case 2: /* 2 lanes */
644 pciercx_cfg448.s.rtl = 867;
645 break;
646 case 4: /* 4 lanes */
647 pciercx_cfg448.s.rtl = 462;
648 break;
649 case 8: /* 8 lanes */
650 pciercx_cfg448.s.rtl = 258;
651 break;
652 }
653 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
654 pciercx_cfg448.u32);
655
656 return 0;
657}
658
659/**
660 * Initialize a PCIe port for use in host(RC) mode. It doesn't
661 * enumerate the bus.
662 *
663 * @pcie_port: PCIe port to initialize
664 *
665 * Returns Zero on success
666 */
667static int cvmx_pcie_rc_initialize(int pcie_port)
668{
669 int i;
670 union cvmx_ciu_soft_prst ciu_soft_prst;
671 union cvmx_pescx_bist_status pescx_bist_status;
672 union cvmx_pescx_bist_status2 pescx_bist_status2;
673 union cvmx_npei_ctl_status npei_ctl_status;
674 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
675 union cvmx_npei_mem_access_subidx mem_access_subid;
676 union cvmx_npei_dbg_data npei_dbg_data;
677 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
678
679 /*
680 * Make sure we aren't trying to setup a target mode interface
681 * in host mode.
682 */
683 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
684 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
685 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
686 "on port0, but port0 is not in host mode\n");
687 return -1;
688 }
689
690 /*
691 * Make sure a CN52XX isn't trying to bring up port 1 when it
692 * is disabled.
693 */
694 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
695 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
696 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
697 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
698 "called on port1, but port1 is "
699 "disabled\n");
700 return -1;
701 }
702 }
703
704 /*
705 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
706 * PCIe0, then PCIe1. '1' == round robin.
707 */
708 npei_ctl_status.s.arb = 1;
709 /* Allow up to 0x20 config retries */
710 npei_ctl_status.s.cfg_rtry = 0x20;
711 /*
712 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
713 * don't reset.
714 */
715 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
716 npei_ctl_status.s.p0_ntags = 0x20;
717 npei_ctl_status.s.p1_ntags = 0x20;
718 }
719 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
720
721 /* Bring the PCIe out of reset */
722 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
723 /*
724 * The EBH5200 board swapped the PCIe reset lines on
725 * the board. As a workaround for this bug, we bring
726 * both PCIe ports out of reset at the same time
727 * instead of on separate calls. So for port 0, we
728 * bring both out of reset and do nothing on port 1.
729 */
730 if (pcie_port == 0) {
731 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
732 /*
733 * After a chip reset the PCIe will also be in
734 * reset. If it isn't, most likely someone is
735 * trying to init it again without a proper
736 * PCIe reset.
737 */
738 if (ciu_soft_prst.s.soft_prst == 0) {
739 /* Reset the ports */
740 ciu_soft_prst.s.soft_prst = 1;
741 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
742 ciu_soft_prst.u64);
743 ciu_soft_prst.u64 =
744 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
745 ciu_soft_prst.s.soft_prst = 1;
746 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
747 ciu_soft_prst.u64);
748 /* Wait until pcie resets the ports. */
749 udelay(2000);
750 }
751 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
752 ciu_soft_prst.s.soft_prst = 0;
753 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
754 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
755 ciu_soft_prst.s.soft_prst = 0;
756 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
757 }
758 } else {
759 /*
760 * The normal case: The PCIe ports are completely
761 * separate and can be brought out of reset
762 * independently.
763 */
764 if (pcie_port)
765 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
766 else
767 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
768 /*
769 * After a chip reset the PCIe will also be in
770 * reset. If it isn't, most likely someone is trying
771 * to init it again without a proper PCIe reset.
772 */
773 if (ciu_soft_prst.s.soft_prst == 0) {
774 /* Reset the port */
775 ciu_soft_prst.s.soft_prst = 1;
776 if (pcie_port)
777 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
778 ciu_soft_prst.u64);
779 else
780 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
781 ciu_soft_prst.u64);
782 /* Wait until pcie resets the ports. */
783 udelay(2000);
784 }
785 if (pcie_port) {
786 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
787 ciu_soft_prst.s.soft_prst = 0;
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
789 } else {
790 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
791 ciu_soft_prst.s.soft_prst = 0;
792 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
793 }
794 }
795
796 /*
797 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
798 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
799 * fixed number of cycles.
800 */
801 cvmx_wait(400000);
802
803 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
804 CN52XX, so we only probe it on newer chips */
805 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
806 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
807 /* Clear PCLK_RUN so we can check if the clock is running */
808 pescx_ctl_status2.u64 =
809 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
810 pescx_ctl_status2.s.pclk_run = 1;
811 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
812 pescx_ctl_status2.u64);
813 /*
814 * Now that we cleared PCLK_RUN, wait for it to be set
815 * again telling us the clock is running.
816 */
817 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
818 union cvmx_pescx_ctl_status2,
819 pclk_run, ==, 1, 10000)) {
820 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
821 pcie_port);
822 return -1;
823 }
824 }
825
826 /*
827 * Check and make sure PCIe came out of reset. If it doesn't
828 * the board probably hasn't wired the clocks up and the
829 * interface should be skipped.
830 */
831 pescx_ctl_status2.u64 =
832 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
833 if (pescx_ctl_status2.s.pcierst) {
834 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
835 pcie_port);
836 return -1;
837 }
838
839 /*
840 * Check BIST2 status. If any bits are set skip this interface. This
841 * is an attempt to catch PCIE-813 on pass 1 parts.
842 */
843 pescx_bist_status2.u64 =
844 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
845 if (pescx_bist_status2.u64) {
846 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
847 "port isn't hooked up, skipping.\n",
848 pcie_port);
849 return -1;
850 }
851
852 /* Check BIST status */
853 pescx_bist_status.u64 =
854 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
855 if (pescx_bist_status.u64)
856 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
857 pcie_port, CAST64(pescx_bist_status.u64));
858
859 /* Initialize the config space CSRs */
860 __cvmx_pcie_rc_initialize_config_space(pcie_port);
861
862 /* Bring the link up */
863 if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
864 cvmx_dprintf
865 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
866 return -1;
867 }
868
869 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
870 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
871 /* Allow 16 words to combine */
872 npei_mem_access_ctl.s.max_word = 0;
873 /* Wait up to 127 cycles for more data */
874 npei_mem_access_ctl.s.timer = 127;
875 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
876
877 /* Setup Mem access SubDIDs */
878 mem_access_subid.u64 = 0;
879 /* Port the request is sent to. */
880 mem_access_subid.s.port = pcie_port;
881 /* Due to an errata on pass 1 chips, no merging is allowed. */
882 mem_access_subid.s.nmerge = 1;
883 /* Endian-swap for Reads. */
884 mem_access_subid.s.esr = 1;
885 /* Endian-swap for Writes. */
886 mem_access_subid.s.esw = 1;
887 /* No Snoop for Reads. */
888 mem_access_subid.s.nsr = 1;
889 /* No Snoop for Writes. */
890 mem_access_subid.s.nsw = 1;
891 /* Disable Relaxed Ordering for Reads. */
892 mem_access_subid.s.ror = 0;
893 /* Disable Relaxed Ordering for Writes. */
894 mem_access_subid.s.row = 0;
895 /* PCIe Adddress Bits <63:34>. */
896 mem_access_subid.s.ba = 0;
897
898 /*
899 * Setup mem access 12-15 for port 0, 16-19 for port 1,
900 * supplying 36 bits of address space.
901 */
902 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
903 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
904 mem_access_subid.u64);
905 /* Set each SUBID to extend the addressable range */
906 mem_access_subid.s.ba += 1;
907 }
908
909 /*
910 * Disable the peer to peer forwarding register. This must be
911 * setup by the OS after it enumerates the bus and assigns
912 * addresses to the PCIe busses.
913 */
914 for (i = 0; i < 4; i++) {
915 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
916 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
917 }
918
919 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
920 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
921
922 /*
923 * Disable Octeon's BAR1. It isn't needed in RC mode since
924 * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
925 * the 2nd 256MB of memory.
926 */
927 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
928
929 /*
930 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
931 * precedence where they overlap. It also overlaps with the
932 * device addresses, so make sure the peer to peer forwarding
933 * is set right.
934 */
935 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
936
937 /*
938 * Setup BAR2 attributes
939 *
940 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
941 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
942 * - WAIT_COM=0 will likely work for all applications.
943 *
944 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
945 */
946 if (pcie_port) {
947 union cvmx_npei_ctl_port1 npei_ctl_port;
948 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
949 npei_ctl_port.s.bar2_enb = 1;
950 npei_ctl_port.s.bar2_esx = 1;
951 npei_ctl_port.s.bar2_cax = 0;
952 npei_ctl_port.s.ptlp_ro = 1;
953 npei_ctl_port.s.ctlp_ro = 1;
954 npei_ctl_port.s.wait_com = 0;
955 npei_ctl_port.s.waitl_com = 0;
956 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
957 } else {
958 union cvmx_npei_ctl_port0 npei_ctl_port;
959 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
960 npei_ctl_port.s.bar2_enb = 1;
961 npei_ctl_port.s.bar2_esx = 1;
962 npei_ctl_port.s.bar2_cax = 0;
963 npei_ctl_port.s.ptlp_ro = 1;
964 npei_ctl_port.s.ctlp_ro = 1;
965 npei_ctl_port.s.wait_com = 0;
966 npei_ctl_port.s.waitl_com = 0;
967 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
968 }
969 return 0;
970}
971
972
973/* Above was cvmx-pcie.c, below original pcie.c */
974
975
976/**
977 * Map a PCI device to the appropriate interrupt line
978 *
979 * @param dev The Linux PCI device structure for the device to map
980 * @param slot The slot number for this device on __BUS 0__. Linux
981 * enumerates through all the bridges and figures out the
982 * slot on Bus 0 where this device eventually hooks to.
983 * @param pin The PCI interrupt pin read from the device, then swizzled
984 * as it goes through each bridge.
985 * @return Interrupt number for the device
986 */
987int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
988 u8 slot, u8 pin)
989{
990 /*
991 * The EBH5600 board with the PCI to PCIe bridge mistakenly
992 * wires the first slot for both device id 2 and interrupt
993 * A. According to the PCI spec, device id 2 should be C. The
994 * following kludge attempts to fix this.
995 */
996 if (strstr(octeon_board_type_string(), "EBH5600") &&
997 dev->bus && dev->bus->parent) {
998 /*
999 * Iterate all the way up the device chain and find
1000 * the root bus.
1001 */
1002 while (dev->bus && dev->bus->parent)
1003 dev = to_pci_dev(dev->bus->bridge);
1004 /* If the root bus is number 0 and the PEX 8114 is the
1005 * root, assume we are behind the miswired bus. We
1006 * need to correct the swizzle level by two. Yuck.
1007 */
1008 if ((dev->bus->number == 0) &&
1009 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1010 /*
1011 * The pin field is one based, not zero. We
1012 * need to swizzle it by minus two.
1013 */
1014 pin = ((pin - 3) & 3) + 1;
1015 }
1016 }
1017 /*
1018 * The -1 is because pin starts with one, not zero. It might
1019 * be that this equation needs to include the slot number, but
1020 * I don't have hardware to check that against.
1021 */
1022 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1023}
1024
1025/**
1026 * Read a value from configuration space
1027 *
1028 * @param bus
1029 * @param devfn
1030 * @param reg
1031 * @param size
1032 * @param val
1033 * @return
1034 */
1035static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1036 unsigned int devfn, int reg, int size,
1037 u32 *val)
1038{
1039 union octeon_cvmemctl cvmmemctl;
1040 union octeon_cvmemctl cvmmemctl_save;
1041 int bus_number = bus->number;
1042
1043 /*
1044 * We need to force the bus number to be zero on the root
1045 * bus. Linux numbers the 2nd root bus to start after all
1046 * buses on root 0.
1047 */
1048 if (bus->parent == NULL)
1049 bus_number = 0;
1050
1051 /*
1052 * PCIe only has a single device connected to Octeon. It is
1053 * always device ID 0. Don't bother doing reads for other
1054 * device IDs on the first segment.
1055 */
1056 if ((bus_number == 0) && (devfn >> 3 != 0))
1057 return PCIBIOS_FUNC_NOT_SUPPORTED;
1058
1059 /*
1060 * The following is a workaround for the CN57XX, CN56XX,
1061 * CN55XX, and CN54XX errata with PCIe config reads from non
1062 * existent devices. These chips will hang the PCIe link if a
1063 * config read is performed that causes a UR response.
1064 */
1065 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1066 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1067 /*
1068 * For our EBH5600 board, port 0 has a bridge with two
1069 * PCI-X slots. We need a new special checks to make
1070 * sure we only probe valid stuff. The PCIe->PCI-X
1071 * bridge only respondes to device ID 0, function
1072 * 0-1
1073 */
1074 if ((bus_number == 0) && (devfn >= 2))
1075 return PCIBIOS_FUNC_NOT_SUPPORTED;
1076 /*
1077 * The PCI-X slots are device ID 2,3. Choose one of
1078 * the below "if" blocks based on what is plugged into
1079 * the board.
1080 */
1081#if 1
1082 /* Use this option if you aren't using either slot */
1083 if (bus_number == 1)
1084 return PCIBIOS_FUNC_NOT_SUPPORTED;
1085#elif 0
1086 /*
1087 * Use this option if you are using the first slot but
1088 * not the second.
1089 */
1090 if ((bus_number == 1) && (devfn >> 3 != 2))
1091 return PCIBIOS_FUNC_NOT_SUPPORTED;
1092#elif 0
1093 /*
1094 * Use this option if you are using the second slot
1095 * but not the first.
1096 */
1097 if ((bus_number == 1) && (devfn >> 3 != 3))
1098 return PCIBIOS_FUNC_NOT_SUPPORTED;
1099#elif 0
1100 /* Use this opion if you are using both slots */
1101 if ((bus_number == 1) &&
1102 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1103 return PCIBIOS_FUNC_NOT_SUPPORTED;
1104#endif
1105
1106 /*
1107 * Shorten the DID timeout so bus errors for PCIe
1108 * config reads from non existent devices happen
1109 * faster. This allows us to continue booting even if
1110 * the above "if" checks are wrong. Once one of these
1111 * errors happens, the PCIe port is dead.
1112 */
1113 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1114 cvmmemctl.u64 = cvmmemctl_save.u64;
1115 cvmmemctl.s.didtto = 2;
1116 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1117 }
1118
1119 switch (size) {
1120 case 4:
1121 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1122 devfn >> 3, devfn & 0x7, reg);
1123 break;
1124 case 2:
1125 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1126 devfn >> 3, devfn & 0x7, reg);
1127 break;
1128 case 1:
1129 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
1130 devfn & 0x7, reg);
1131 break;
1132 default:
1133 return PCIBIOS_FUNC_NOT_SUPPORTED;
1134 }
1135
1136 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1137 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1138 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
1139 return PCIBIOS_SUCCESSFUL;
1140}
1141
1142static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1143 int reg, int size, u32 *val)
1144{
1145 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1146}
1147
1148static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1149 int reg, int size, u32 *val)
1150{
1151 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1152}
1153
1154
1155
1156/**
1157 * Write a value to PCI configuration space
1158 *
1159 * @param bus
1160 * @param devfn
1161 * @param reg
1162 * @param size
1163 * @param val
1164 * @return
1165 */
1166static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1167 unsigned int devfn, int reg,
1168 int size, u32 val)
1169{
1170 int bus_number = bus->number;
1171 /*
1172 * We need to force the bus number to be zero on the root
1173 * bus. Linux numbers the 2nd root bus to start after all
1174 * busses on root 0.
1175 */
1176 if (bus->parent == NULL)
1177 bus_number = 0;
1178
1179 switch (size) {
1180 case 4:
1181 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1182 devfn & 0x7, reg, val);
1183 return PCIBIOS_SUCCESSFUL;
1184 case 2:
1185 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1186 devfn & 0x7, reg, val);
1187 return PCIBIOS_SUCCESSFUL;
1188 case 1:
1189 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1190 devfn & 0x7, reg, val);
1191 return PCIBIOS_SUCCESSFUL;
1192 }
1193#if PCI_CONFIG_SPACE_DELAY
1194 udelay(PCI_CONFIG_SPACE_DELAY);
1195#endif
1196 return PCIBIOS_FUNC_NOT_SUPPORTED;
1197}
1198
1199static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1200 int reg, int size, u32 val)
1201{
1202 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1203}
1204
1205static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1206 int reg, int size, u32 val)
1207{
1208 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1209}
1210
1211static struct pci_ops octeon_pcie0_ops = {
1212 octeon_pcie0_read_config,
1213 octeon_pcie0_write_config,
1214};
1215
1216static struct resource octeon_pcie0_mem_resource = {
1217 .name = "Octeon PCIe0 MEM",
1218 .flags = IORESOURCE_MEM,
1219};
1220
1221static struct resource octeon_pcie0_io_resource = {
1222 .name = "Octeon PCIe0 IO",
1223 .flags = IORESOURCE_IO,
1224};
1225
1226static struct pci_controller octeon_pcie0_controller = {
1227 .pci_ops = &octeon_pcie0_ops,
1228 .mem_resource = &octeon_pcie0_mem_resource,
1229 .io_resource = &octeon_pcie0_io_resource,
1230};
1231
1232static struct pci_ops octeon_pcie1_ops = {
1233 octeon_pcie1_read_config,
1234 octeon_pcie1_write_config,
1235};
1236
1237static struct resource octeon_pcie1_mem_resource = {
1238 .name = "Octeon PCIe1 MEM",
1239 .flags = IORESOURCE_MEM,
1240};
1241
1242static struct resource octeon_pcie1_io_resource = {
1243 .name = "Octeon PCIe1 IO",
1244 .flags = IORESOURCE_IO,
1245};
1246
1247static struct pci_controller octeon_pcie1_controller = {
1248 .pci_ops = &octeon_pcie1_ops,
1249 .mem_resource = &octeon_pcie1_mem_resource,
1250 .io_resource = &octeon_pcie1_io_resource,
1251};
1252
1253
1254/**
1255 * Initialize the Octeon PCIe controllers
1256 *
1257 * @return
1258 */
1259static int __init octeon_pcie_setup(void)
1260{
1261 union cvmx_npei_ctl_status npei_ctl_status;
1262 int result;
1263
1264 /* These chips don't have PCIe */
1265 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1266 return 0;
1267
1268 /* Point pcibios_map_irq() to the PCIe version of it */
1269 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1270
1271 /* Use the PCIe based DMA mappings */
1272 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1273
1274 /*
1275 * PCIe I/O range. It is based on port 0 but includes up until
1276 * port 1's end.
1277 */
1278 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1279 ioport_resource.start = 0;
1280 ioport_resource.end =
1281 cvmx_pcie_get_io_base_address(1) -
1282 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1283
1284 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1285 if (npei_ctl_status.s.host_mode) {
1286 pr_notice("PCIe: Initializing port 0\n");
1287 result = cvmx_pcie_rc_initialize(0);
1288 if (result == 0) {
1289 /* Memory offsets are physical addresses */
1290 octeon_pcie0_controller.mem_offset =
1291 cvmx_pcie_get_mem_base_address(0);
1292 /* IO offsets are Mips virtual addresses */
1293 octeon_pcie0_controller.io_map_base =
1294 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1295 (0));
1296 octeon_pcie0_controller.io_offset = 0;
1297 /*
1298 * To keep things similar to PCI, we start
1299 * device addresses at the same place as PCI
1300 * uisng big bar support. This normally
1301 * translates to 4GB-256MB, which is the same
1302 * as most x86 PCs.
1303 */
1304 octeon_pcie0_controller.mem_resource->start =
1305 cvmx_pcie_get_mem_base_address(0) +
1306 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1307 octeon_pcie0_controller.mem_resource->end =
1308 cvmx_pcie_get_mem_base_address(0) +
1309 cvmx_pcie_get_mem_size(0) - 1;
1310 /*
1311 * Ports must be above 16KB for the ISA bus
1312 * filtering in the PCI-X to PCI bridge.
1313 */
1314 octeon_pcie0_controller.io_resource->start = 4 << 10;
1315 octeon_pcie0_controller.io_resource->end =
1316 cvmx_pcie_get_io_size(0) - 1;
1317 register_pci_controller(&octeon_pcie0_controller);
1318 }
1319 } else {
1320 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1321 }
1322
1323 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1324 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1325 union cvmx_npei_dbg_data npei_dbg_data;
1326 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1327 if (npei_dbg_data.cn52xx.qlm0_link_width)
1328 return 0;
1329 }
1330
1331 pr_notice("PCIe: Initializing port 1\n");
1332 result = cvmx_pcie_rc_initialize(1);
1333 if (result == 0) {
1334 /* Memory offsets are physical addresses */
1335 octeon_pcie1_controller.mem_offset =
1336 cvmx_pcie_get_mem_base_address(1);
1337 /* IO offsets are Mips virtual addresses */
1338 octeon_pcie1_controller.io_map_base =
1339 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1340 octeon_pcie1_controller.io_offset =
1341 cvmx_pcie_get_io_base_address(1) -
1342 cvmx_pcie_get_io_base_address(0);
1343 /*
1344 * To keep things similar to PCI, we start device
1345 * addresses at the same place as PCI uisng big bar
1346 * support. This normally translates to 4GB-256MB,
1347 * which is the same as most x86 PCs.
1348 */
1349 octeon_pcie1_controller.mem_resource->start =
1350 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1351 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1352 octeon_pcie1_controller.mem_resource->end =
1353 cvmx_pcie_get_mem_base_address(1) +
1354 cvmx_pcie_get_mem_size(1) - 1;
1355 /*
1356 * Ports must be above 16KB for the ISA bus filtering
1357 * in the PCI-X to PCI bridge.
1358 */
1359 octeon_pcie1_controller.io_resource->start =
1360 cvmx_pcie_get_io_base_address(1) -
1361 cvmx_pcie_get_io_base_address(0);
1362 octeon_pcie1_controller.io_resource->end =
1363 octeon_pcie1_controller.io_resource->start +
1364 cvmx_pcie_get_io_size(1) - 1;
1365 register_pci_controller(&octeon_pcie1_controller);
1366 }
1367 return 0;
1368}
1369
1370arch_initcall(octeon_pcie_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 10:45:14 -0500