diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-03-02 10:44:16 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-03-02 10:44:16 -0500 |
| commit | aebb2afd5420c860b7fbc3882a323ef1247fbf16 (patch) | |
| tree | 05ee0efcebca5ec421de44de7a6d6271088c64a8 /arch/mips/cavium-octeon/octeon-memcpy.S | |
| parent | 8eae508b7c6ff502a71d0293b69e97c5505d5840 (diff) | |
| parent | edb15d83a875a1f4b1576188844db5c330c3267d (diff) | |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
o Add basic support for the Mediatek/Ralink Wireless SoC family.
o The Qualcomm Atheros platform is extended by support for the new
QCA955X SoC series as well as a bunch of patches that get the code
ready for OF support.
o Lantiq and BCM47XX platform have a few improvements and bug fixes.
o MIPS has sent a few patches that get the kernel ready for the
upcoming microMIPS support.
o The rest of the series is made up of small bug fixes and cleanups
that relate to various parts of the MIPS code. The biggy in there is
a whitespace cleanup. After I was sent another set of whitespace
cleanup patches I decided it was the time to clean the whitespace
"issues" for once and and that touches many files below arch/mips/.
Fix up silly conflicts, mostly due to whitespace cleanups.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
MIPS: remove broken conditional inside vpe loader code
MIPS: SMTC: fix implicit declaration of set_vi_handler
MIPS: early_printk: drop __init annotations
MIPS: Probe for and report hardware virtualization support.
MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
MIPS: ath79: add USB controller registration code for the QCA955X SoCs
MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
MIPS: ath79: add WMAC registration code for the QCA955X SoCs
MIPS: ath79: register UART for the QCA955X SoCs
MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
MIPS: ath79: add GPIO setup code for the QCA955X SoCs
MIPS: ath79: add IRQ handling code for the QCA955X SoCs
MIPS: ath79: add clock setup code for the QCA955X SoCs
MIPS: ath79: add SoC detection code for the QCA955X SoCs
MIPS: ath79: add early printk support for the QCA955X SoCs
MIPS: ath79: fix WMAC IRQ resource assignment
mips: reserve elfcorehdr
mips: Make sure kernel memory is in iomem
MIPS: ath79: use dynamically allocated USB platform devices
...
Diffstat (limited to 'arch/mips/cavium-octeon/octeon-memcpy.S')
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-memcpy.S | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S index 0ba0eb96d9ac..64e08df51d65 100644 --- a/arch/mips/cavium-octeon/octeon-memcpy.S +++ b/arch/mips/cavium-octeon/octeon-memcpy.S | |||
| @@ -116,15 +116,15 @@ | |||
| 116 | 116 | ||
| 117 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | 117 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 118 | #define LDFIRST LOADR | 118 | #define LDFIRST LOADR |
| 119 | #define LDREST LOADL | 119 | #define LDREST LOADL |
| 120 | #define STFIRST STORER | 120 | #define STFIRST STORER |
| 121 | #define STREST STOREL | 121 | #define STREST STOREL |
| 122 | #define SHIFT_DISCARD SLLV | 122 | #define SHIFT_DISCARD SLLV |
| 123 | #else | 123 | #else |
| 124 | #define LDFIRST LOADL | 124 | #define LDFIRST LOADL |
| 125 | #define LDREST LOADR | 125 | #define LDREST LOADR |
| 126 | #define STFIRST STOREL | 126 | #define STFIRST STOREL |
| 127 | #define STREST STORER | 127 | #define STREST STORER |
| 128 | #define SHIFT_DISCARD SRLV | 128 | #define SHIFT_DISCARD SRLV |
| 129 | #endif | 129 | #endif |
| 130 | 130 | ||
| @@ -316,9 +316,9 @@ EXC( STORE t0, -8(dst), s_exc_p1u) | |||
| 316 | 316 | ||
| 317 | src_unaligned: | 317 | src_unaligned: |
| 318 | #define rem t8 | 318 | #define rem t8 |
| 319 | SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter | 319 | SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter |
| 320 | beqz t0, cleanup_src_unaligned | 320 | beqz t0, cleanup_src_unaligned |
| 321 | and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES | 321 | and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES |
| 322 | 1: | 322 | 1: |
| 323 | /* | 323 | /* |
| 324 | * Avoid consecutive LD*'s to the same register since some mips | 324 | * Avoid consecutive LD*'s to the same register since some mips |
| @@ -326,13 +326,13 @@ src_unaligned: | |||
| 326 | * It's OK to load FIRST(N+1) before REST(N) because the two addresses | 326 | * It's OK to load FIRST(N+1) before REST(N) because the two addresses |
| 327 | * are to the same unit (unless src is aligned, but it's not). | 327 | * are to the same unit (unless src is aligned, but it's not). |
| 328 | */ | 328 | */ |
| 329 | EXC( LDFIRST t0, FIRST(0)(src), l_exc) | 329 | EXC( LDFIRST t0, FIRST(0)(src), l_exc) |
| 330 | EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) | 330 | EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) |
| 331 | SUB len, len, 4*NBYTES | 331 | SUB len, len, 4*NBYTES |
| 332 | EXC( LDREST t0, REST(0)(src), l_exc_copy) | 332 | EXC( LDREST t0, REST(0)(src), l_exc_copy) |
| 333 | EXC( LDREST t1, REST(1)(src), l_exc_copy) | 333 | EXC( LDREST t1, REST(1)(src), l_exc_copy) |
| 334 | EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) | 334 | EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) |
| 335 | EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) | 335 | EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) |
| 336 | EXC( LDREST t2, REST(2)(src), l_exc_copy) | 336 | EXC( LDREST t2, REST(2)(src), l_exc_copy) |
| 337 | EXC( LDREST t3, REST(3)(src), l_exc_copy) | 337 | EXC( LDREST t3, REST(3)(src), l_exc_copy) |
| 338 | ADD src, src, 4*NBYTES | 338 | ADD src, src, 4*NBYTES |