MIPS: Cavium: Add CPU hotplugging code.

Thanks to Cavium Inc. for the code contribution and help.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 59 insertions, 0 deletions

diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 3090ee37e109..384f1842bfb1 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -501,3 +501,62 @@ asmlinkage void plat_irq_dispatch(void)
                 }
         }
 }
+
+#ifdef CONFIG_HOTPLUG_CPU
+static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
+{
+       unsigned int isset;
+#ifdef CONFIG_SMP
+       int coreid = cpu_logical_map(cpu);
+#else
+        int coreid = cvmx_get_core_num();
+#endif
+        int bit = (irq < OCTEON_IRQ_WDOG0) ?
+                irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
+       if (irq < 64) {
+                isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
+                        (1ull << bit)) >> bit;
+       } else {
+               isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
+                        (1ull << bit)) >> bit;
+       }
+       return isset;
+}
+
+void fixup_irqs(void)
+{
+       int irq;
+
+        for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
+                octeon_irq_core_disable_local(irq);
+
+        for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
+                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
+                        /* ciu irq migrates to next cpu */
+                        octeon_irq_chip_ciu0.disable(irq);
+                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
+                }
+        }
+
+#if 0
+        for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
+                octeon_irq_mailbox_mask(irq);
+#endif
+        for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
+                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
+                        /* ciu irq migrates to next cpu */
+                        octeon_irq_chip_ciu0.disable(irq);
+                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
+                }
+        }
+
+        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
+                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
+                        /* ciu irq migrates to next cpu */
+                        octeon_irq_chip_ciu1.disable(irq);
+                        octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
+                }
+        }
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */