MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.

These are the rest of the new files needed to add OCTEON processor
support to the Linux kernel.  Other than Makefile and Kconfig which
should be obvious, we have:

csrc-octeon.c   -- Clock source driver for OCTEON.
dma-octeon.c    -- Helper functions for mapping DMA memory.
flash_setup.c   -- Register on-board flash with the MTD subsystem.
octeon-irq.c    -- OCTEON interrupt controller managment.
octeon-memcpy.S -- Optimized memcpy() implementation.
serial.c        -- Register 8250 platform driver and early console.
setup.c         -- Early architecture initialization.
smp.c           -- OCTEON SMP support.
octeon_switch.S -- Scheduler context switch for OCTEON.
c-octeon.c      -- OCTEON cache controller support.
cex-oct.S       -- OCTEON cache exception handler.

asm/mach-cavium-octeon/*.h -- Architecture include files.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 arch/mips/cavium-octeon/Kconfig
 create mode 100644 arch/mips/cavium-octeon/Makefile
 create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c
 create mode 100644 arch/mips/cavium-octeon/dma-octeon.c
 create mode 100644 arch/mips/cavium-octeon/flash_setup.c
 create mode 100644 arch/mips/cavium-octeon/octeon-irq.c
 create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S
 create mode 100644 arch/mips/cavium-octeon/serial.c
 create mode 100644 arch/mips/cavium-octeon/setup.c
 create mode 100644 arch/mips/cavium-octeon/smp.c
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
 create mode 100644 arch/mips/include/asm/octeon/octeon.h
 create mode 100644 arch/mips/kernel/octeon_switch.S
 create mode 100644 arch/mips/mm/c-octeon.c
 create mode 100644 arch/mips/mm/cex-oct.S

1 files changed, 84 insertions, 0 deletions

diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
new file mode 100644
index 000000000000..553d36cbcc42
--- /dev/null
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -0,0 +1,84 @@
+/*
+ *   Octeon Bootbus flash setup
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007, 2008 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/octeon/octeon.h>
+
+static struct map_info flash_map;
+static struct mtd_info *mymtd;
+#ifdef CONFIG_MTD_PARTITIONS
+static int nr_parts;
+static struct mtd_partition *parts;
+static const char *part_probe_types[] = {
+        "cmdlinepart",
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+        "RedBoot",
+#endif
+        NULL
+};
+#endif
+
+/**
+ * Module/ driver initialization.
+ *
+ * Returns Zero on success
+ */
+static int __init flash_init(void)
+{
+        /*
+         * Read the bootbus region 0 setup to determine the base
+         * address of the flash.
+         */
+        union cvmx_mio_boot_reg_cfgx region_cfg;
+        region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0));
+        if (region_cfg.s.en) {
+                /*
+                 * The bootloader always takes the flash and sets its
+                 * address so the entire flash fits below
+                 * 0x1fc00000. This way the flash aliases to
+                 * 0x1fc00000 for booting. Software can access the
+                 * full flash at the true address, while core boot can
+                 * access 4MB.
+                 */
+                /* Use this name so old part lines work */
+                flash_map.name = "phys_mapped_flash";
+                flash_map.phys = region_cfg.s.base << 16;
+                flash_map.size = 0x1fc00000 - flash_map.phys;
+                flash_map.bankwidth = 1;
+                flash_map.virt = ioremap(flash_map.phys, flash_map.size);
+                pr_notice("Bootbus flash: Setting flash for %luMB flash at "
+                          "0x%08lx\n", flash_map.size >> 20, flash_map.phys);
+                simple_map_init(&flash_map);
+                mymtd = do_map_probe("cfi_probe", &flash_map);
+                if (mymtd) {
+                        mymtd->owner = THIS_MODULE;
+
+#ifdef CONFIG_MTD_PARTITIONS
+                        nr_parts = parse_mtd_partitions(mymtd,
+                                                        part_probe_types,
+                                                        &parts, 0);
+                        if (nr_parts > 0)
+                                add_mtd_partitions(mymtd, parts, nr_parts);
+                        else
+                                add_mtd_device(mymtd);
+#else
+                        add_mtd_device(mymtd);
+#endif
+                } else {
+                        pr_err("Failed to register MTD device for flash\n");
+                }
+        }
+        return 0;
+}
+
+late_initcall(flash_init);