Merge branch 'tracing/core' into tracing/hw-breakpoints

Conflicts:
	arch/Kconfig
	kernel/trace/trace.h

Merge reason: resolve the conflicts, plus adopt to the new
              ring-buffer APIs.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

5 files changed, 324 insertions, 0 deletions

diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 80d6cb26766b..2fd66db6939e 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -11,3 +11,4 @@
 
 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
 
+obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 4f5a08b37ccd..25666da17b22 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -31,6 +31,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-spinlock.h>
@@ -97,6 +98,33 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
         return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
 }
 
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+                                     uint64_t max_addr, uint64_t align,
+                                     char *name)
+{
+        int64_t addr;
+
+        addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
+                                                  align, name, 0);
+        if (addr >= 0)
+                return cvmx_phys_to_ptr(addr);
+        else
+                return NULL;
+}
+
+void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+                                       char *name)
+{
+    return cvmx_bootmem_alloc_named_range(size, address, address + size,
+                                          0, name);
+}
+
+void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
+{
+    return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name);
+}
+EXPORT_SYMBOL(cvmx_bootmem_alloc_named);
+
 int cvmx_bootmem_free_named(char *name)
 {
         return cvmx_bootmem_phy_named_block_free(name, 0);
@@ -106,6 +134,7 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name)
 {
         return cvmx_bootmem_phy_named_block_find(name, 0);
 }
+EXPORT_SYMBOL(cvmx_bootmem_find_named_block);
 
 void cvmx_bootmem_lock(void)
 {
@@ -584,3 +613,78 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
         cvmx_bootmem_unlock();
         return named_block_ptr != NULL; /* 0 on failure, 1 on success */
 }
+
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+                                           uint64_t max_addr,
+                                           uint64_t alignment,
+                                           char *name,
+                                           uint32_t flags)
+{
+        int64_t addr_allocated;
+        struct cvmx_bootmem_named_block_desc *named_block_desc_ptr;
+
+#ifdef DEBUG
+        cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: "
+                     "0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
+                     (unsigned long long)size,
+                     (unsigned long long)min_addr,
+                     (unsigned long long)max_addr,
+                     (unsigned long long)alignment,
+                     name);
+#endif
+        if (cvmx_bootmem_desc->major_version != 3) {
+                cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
+                             "%d.%d at addr: %p\n",
+                             (int)cvmx_bootmem_desc->major_version,
+                             (int)cvmx_bootmem_desc->minor_version,
+                             cvmx_bootmem_desc);
+                return -1;
+        }
+
+        /*
+         * Take lock here, as name lookup/block alloc/name add need to
+         * be atomic.
+         */
+        if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+        /* Get pointer to first available named block descriptor */
+        named_block_desc_ptr =
+                cvmx_bootmem_phy_named_block_find(NULL,
+                                                  flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+        /*
+         * Check to see if name already in use, return error if name
+         * not available or no more room for blocks.
+         */
+        if (cvmx_bootmem_phy_named_block_find(name,
+                                              flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr) {
+                if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+                return -1;
+        }
+
+
+        /*
+         * Round size up to mult of minimum alignment bytes We need
+         * the actual size allocated to allow for blocks to be
+         * coallesced when they are freed.  The alloc routine does the
+         * same rounding up on all allocations.
+         */
+        size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1));
+
+        addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr,
+                                                alignment,
+                                                flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+        if (addr_allocated >= 0) {
+                named_block_desc_ptr->base_addr = addr_allocated;
+                named_block_desc_ptr->size = size;
+                strncpy(named_block_desc_ptr->name, name,
+                        cvmx_bootmem_desc->named_block_name_len);
+                named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
+        }
+
+        if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+        return addr_allocated;
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
new file mode 100644
index 000000000000..868659e64d4a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -0,0 +1,73 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Fixes and workaround for Octeon chip errata. This file
+ * contains functions called by cvmx-helper to workaround known
+ * chip errata. For the most part, code doesn't need to call
+ * these functions directly.
+ *
+ */
+#include <linux/module.h>
+
+#include <asm/octeon/octeon.h>
+
+#include <asm/octeon/cvmx-helper-jtag.h>
+
+/**
+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
+ * 1 doesn't work properly. The following code disables 2nd order
+ * CDR for the specified QLM.
+ *
+ * @qlm:    QLM to disable 2nd order CDR for.
+ */
+void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
+{
+        int lane;
+        cvmx_helper_qlm_jtag_init();
+        /* We need to load all four lanes of the QLM, a total of 1072 bits */
+        for (lane = 0; lane < 4; lane++) {
+                /*
+                 * Each lane has 268 bits. We need to set
+                 * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
+                 * 1. All other bits are zero. Bits go in LSB first,
+                 * so start off with the zeros for bits <63:0>.
+                 */
+                cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
+                /* cfg_cdr_incx<67:64>=3 */
+                cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
+                /* Zeros for bits <76:68> */
+                cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
+                /* cfg_cdr_secord<77>=1 */
+                cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
+                /* Zeros for bits <267:78> */
+                cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
+        }
+        cvmx_helper_qlm_jtag_update(qlm);
+}
+EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
new file mode 100644
index 000000000000..c1c54890bae0
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -0,0 +1,144 @@
+
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Helper utilities for qlm_jtag.
+ *
+ */
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-helper-jtag.h>
+
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+void cvmx_helper_qlm_jtag_init(void)
+{
+        union cvmx_ciu_qlm_jtgc jtgc;
+        uint32_t clock_div = 0;
+        uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
+        divisor = (divisor - 1) >> 2;
+        /* Convert the divisor into a power of 2 shift */
+        while (divisor) {
+                clock_div++;
+                divisor = divisor >> 1;
+        }
+
+        /*
+         * Clock divider for QLM JTAG operations.  eclk is divided by
+         * 2^(CLK_DIV + 2)
+         */
+        jtgc.u64 = 0;
+        jtgc.s.clk_div = clock_div;
+        jtgc.s.mux_sel = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+                jtgc.s.bypass = 0x3;
+        else
+                jtgc.s.bypass = 0xf;
+        cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+        cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+}
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain is
+ * 4 * 268 bits long, or 1072.
+ *
+ * @qlm:    QLM to shift value into
+ * @bits:   Number of bits to shift in (1-32).
+ * @data:   Data to shift in. Bit 0 enters the chain first, followed by
+ *               bit 1, etc.
+ *
+ * Returns The low order bits of the JTAG chain that shifted out of the
+ *         circle.
+ */
+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
+{
+        union cvmx_ciu_qlm_jtgd jtgd;
+        jtgd.u64 = 0;
+        jtgd.s.shift = 1;
+        jtgd.s.shft_cnt = bits - 1;
+        jtgd.s.shft_reg = data;
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+                jtgd.s.select = 1 << qlm;
+        cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+        do {
+                jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+        } while (jtgd.s.shift);
+        return jtgd.s.shft_reg >> (32 - bits);
+}
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @qlm:    QLM to shift zeros into
+ * @bits:
+ */
+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
+{
+        while (bits > 0) {
+                int n = bits;
+                if (n > 32)
+                        n = 32;
+                cvmx_helper_qlm_jtag_shift(qlm, n, 0);
+                bits -= n;
+        }
+}
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in 268*4, or 1072 bits into the JTAG
+ * chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @qlm:    QLM to program
+ */
+void cvmx_helper_qlm_jtag_update(int qlm)
+{
+        union cvmx_ciu_qlm_jtgd jtgd;
+
+        /* Update the new data */
+        jtgd.u64 = 0;
+        jtgd.s.update = 1;
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+                jtgd.s.select = 1 << qlm;
+        cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+        do {
+                jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+        } while (jtgd.s.update);
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
index 4812370706a1..e5838890cba5 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -29,6 +29,7 @@
  * This module provides system/board/application information obtained
  * by the bootloader.
  */
+#include <linux/module.h>
 
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-spinlock.h>
@@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void)
 {
         return &(state.sysinfo);
 }
+EXPORT_SYMBOL(cvmx_sysinfo_get);
 
 /**
  * This function is used in non-simple executive environments (such as