MIPS: BCM63XX: add basic BCM6362 support

Add basic support for detecting and booting the BCM6362.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5009/
Acked-by: John Crispin <blogic@openwrt.org>

7 files changed, 112 insertions, 4 deletions

diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index d03e8799d1cf..5639662fd503 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
         bool "support 6358 CPU"
         select HW_HAS_PCI
 
+config BCM63XX_CPU_6362
+        bool "support 6362 CPU"
+        select HW_HAS_PCI
+
 config BCM63XX_CPU_6368
         bool "support 6368 CPU"
         select HW_HAS_PCI
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 9aa7d44898ed..a9505c4867e8 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -726,11 +726,11 @@ void __init board_prom_init(void)
         u32 val;
 
         /* read base address of boot chip select (0)
-         * 6328 does not have MPI but boots from a fixed address
+         * 6328/6362 do not have MPI but boot from a fixed address
          */
-        if (BCMCPU_IS_6328())
+        if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
                 val = 0x18000000;
-        else {
+        } else {
                 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
                 val &= MPI_CSBASE_BASE_MASK;
         }
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index fef168d85884..79fe32df5e96 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
 
 };
 
+static const unsigned long bcm6362_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6362)
+};
+
+static const int bcm6362_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6362)
+
+};
+
 static const unsigned long bcm6368_regs_base[] = {
         __GEN_CPU_REGS_TABLE(6368)
 };
@@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(void)
                 return (16 * 1000000 * n1 * n2) / m1;
         }
 
+        case BCM6362_CPU_ID:
+        {
+                unsigned int tmp, mips_pll_fcvo;
+
+                tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
+                mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
+                                >> STRAPBUS_6362_FCVO_SHIFT;
+                switch (mips_pll_fcvo) {
+                case 0x03:
+                case 0x0b:
+                case 0x13:
+                case 0x1b:
+                        return 240000000;
+                case 0x04:
+                case 0x0c:
+                case 0x14:
+                case 0x1c:
+                        return 160000000;
+                case 0x05:
+                case 0x0e:
+                case 0x16:
+                case 0x1e:
+                case 0x1f:
+                        return 400000000;
+                case 0x06:
+                        return 440000000;
+                case 0x07:
+                case 0x17:
+                        return 384000000;
+                case 0x15:
+                case 0x1d:
+                        return 200000000;
+                default:
+                        return 320000000;
+                }
+        }
         case BCM6368_CPU_ID:
         {
                 unsigned int tmp, p1, p2, ndiv, m1;
@@ -205,7 +250,7 @@ static unsigned int detect_memory_size(void)
         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
         u32 val;
 
-        if (BCMCPU_IS_6328())
+        if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
                 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
 
         if (BCMCPU_IS_6345()) {
@@ -297,6 +342,10 @@ void __init bcm63xx_cpu_init(void)
                 bcm63xx_regs_base = bcm6358_regs_base;
                 bcm63xx_irqs = bcm6358_irqs;
                 break;
+        case BCM6362_CPU_ID:
+                bcm63xx_regs_base = bcm6362_regs_base;
+                bcm63xx_irqs = bcm6362_irqs;
+                break;
         case BCM6368_CPU_ID:
                 bcm63xx_regs_base = bcm6368_regs_base;
                 bcm63xx_irqs = bcm6368_irqs;
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index da24c2bd9b7c..c0ab3887f42e 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 #define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6358
 #define ext_irq_cfg_reg2        0
 #endif
+#ifdef CONFIG_BCM63XX_CPU_6362
+#define irq_stat_reg            PERF_IRQSTAT_6362_REG
+#define irq_mask_reg            PERF_IRQMASK_6362_REG
+#define irq_bits                64
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6362
+#define ext_irq_cfg_reg2        0
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6368
 #define irq_stat_reg            PERF_IRQSTAT_6368_REG
 #define irq_mask_reg            PERF_IRQMASK_6368_REG
@@ -170,6 +181,16 @@ static void bcm63xx_init_irq(void)
                 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
                 break;
+        case BCM6362_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6362_REG;
+                irq_mask_addr += PERF_IRQMASK_6362_REG;
+                irq_bits = 64;
+                ext_irq_count = 4;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
+                break;
         case BCM6368_CPU_ID:
                 irq_stat_addr += PERF_IRQSTAT_6368_REG;
                 irq_mask_addr += PERF_IRQMASK_6368_REG;
@@ -458,6 +479,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
         case BCM6338_CPU_ID:
         case BCM6345_CPU_ID:
         case BCM6358_CPU_ID:
+        case BCM6362_CPU_ID:
         case BCM6368_CPU_ID:
                 if (levelsense)
                         reg |= EXTIRQ_CFG_LEVELSENSE(irq);
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 10eaff458071..fd698087fbfd 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -36,6 +36,8 @@ void __init prom_init(void)
                 mask = CKCTL_6348_ALL_SAFE_EN;
         else if (BCMCPU_IS_6358())
                 mask = CKCTL_6358_ALL_SAFE_EN;
+        else if (BCMCPU_IS_6362())
+                mask = CKCTL_6362_ALL_SAFE_EN;
         else if (BCMCPU_IS_6368())
                 mask = CKCTL_6368_ALL_SAFE_EN;
         else
diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
index 68a31bb90cbf..317931c6cf58 100644
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -85,6 +85,20 @@
 #define BCM6358_RESET_PCIE      0
 #define BCM6358_RESET_PCIE_EXT  0
 
+#define BCM6362_RESET_SPI       SOFTRESET_6362_SPI_MASK
+#define BCM6362_RESET_ENET      0
+#define BCM6362_RESET_USBH      SOFTRESET_6362_USBH_MASK
+#define BCM6362_RESET_USBD      SOFTRESET_6362_USBS_MASK
+#define BCM6362_RESET_DSL       0
+#define BCM6362_RESET_SAR       SOFTRESET_6362_SAR_MASK
+#define BCM6362_RESET_EPHY      SOFTRESET_6362_EPHY_MASK
+#define BCM6362_RESET_ENETSW    SOFTRESET_6362_ENETSW_MASK
+#define BCM6362_RESET_PCM       SOFTRESET_6362_PCM_MASK
+#define BCM6362_RESET_MPI       0
+#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
+                                 SOFTRESET_6362_PCIE_CORE_MASK)
+#define BCM6362_RESET_PCIE_EXT  SOFTRESET_6362_PCIE_EXT_MASK
+
 #define BCM6368_RESET_SPI       SOFTRESET_6368_SPI_MASK
 #define BCM6368_RESET_ENET      0
 #define BCM6368_RESET_USBH      SOFTRESET_6368_USBH_MASK
@@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6358)
 };
 
+static const u32 bcm6362_reset_bits[] = {
+        __GEN_RESET_BITS_TABLE(6362)
+};
+
 static const u32 bcm6368_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6368)
 };
@@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_init(void)
         } else if (BCMCPU_IS_6358()) {
                 reset_reg = PERF_SOFTRESET_6358_REG;
                 bcm63xx_reset_bits = bcm6358_reset_bits;
+        } else if (BCMCPU_IS_6362()) {
+                reset_reg = PERF_SOFTRESET_6362_REG;
+                bcm63xx_reset_bits = bcm6362_reset_bits;
         } else if (BCMCPU_IS_6368()) {
                 reset_reg = PERF_SOFTRESET_6368_REG;
                 bcm63xx_reset_bits = bcm6368_reset_bits;
@@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] = {
 #define reset_reg PERF_SOFTRESET_6358_REG
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6362
+static const u32 bcm63xx_reset_bits[] = {
+        __GEN_RESET_BITS_TABLE(6362)
+};
+#define reset_reg PERF_SOFTRESET_6362_REG
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6368
 static const u32 bcm63xx_reset_bits[] = {
         __GEN_RESET_BITS_TABLE(6368)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 911fd7df49e5..24a24445db64 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
         case BCM6358_CPU_ID:
                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
                 break;
+        case BCM6362_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
+                break;
         }
 
         for (i = 0; i < 2; i++) {