diff options
author | Jonas Gorski <jogo@openwrt.org> | 2014-07-12 06:49:37 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-07-30 09:28:34 -0400 |
commit | 3534b5ce0547790429d40b19bb444e099f6ba1cf (patch) | |
tree | 28c572062c13de1ea5028fe53e776fd6afbde1e0 /arch/mips/bcm63xx | |
parent | cc81d7f37273ccb34db99a1f7ce688953a04289d (diff) |
MIPS: BCM63xx: Populate irq_{stat,mask}_addr for second cpu
Set it to zero if there is no second set.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: John Crispin <blogic@openwrt.org>
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Gregory Fong <gregory.0xf0@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7319/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/bcm63xx')
-rw-r--r-- | arch/mips/bcm63xx/irq.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 91d1765561b5..f467e447bb0e 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c | |||
@@ -342,11 +342,15 @@ static void bcm63xx_init_irq(void) | |||
342 | 342 | ||
343 | irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); | 343 | irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); |
344 | irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); | 344 | irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); |
345 | irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); | ||
346 | irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); | ||
345 | 347 | ||
346 | switch (bcm63xx_get_cpu_id()) { | 348 | switch (bcm63xx_get_cpu_id()) { |
347 | case BCM3368_CPU_ID: | 349 | case BCM3368_CPU_ID: |
348 | irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; | 350 | irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; |
349 | irq_mask_addr[0] += PERF_IRQMASK_3368_REG; | 351 | irq_mask_addr[0] += PERF_IRQMASK_3368_REG; |
352 | irq_stat_addr[1] = 0; | ||
353 | irq_stat_addr[1] = 0; | ||
350 | irq_bits = 32; | 354 | irq_bits = 32; |
351 | ext_irq_count = 4; | 355 | ext_irq_count = 4; |
352 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; | 356 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; |
@@ -354,6 +358,8 @@ static void bcm63xx_init_irq(void) | |||
354 | case BCM6328_CPU_ID: | 358 | case BCM6328_CPU_ID: |
355 | irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); | 359 | irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); |
356 | irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); | 360 | irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); |
361 | irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); | ||
362 | irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1); | ||
357 | irq_bits = 64; | 363 | irq_bits = 64; |
358 | ext_irq_count = 4; | 364 | ext_irq_count = 4; |
359 | is_ext_irq_cascaded = 1; | 365 | is_ext_irq_cascaded = 1; |
@@ -364,6 +370,8 @@ static void bcm63xx_init_irq(void) | |||
364 | case BCM6338_CPU_ID: | 370 | case BCM6338_CPU_ID: |
365 | irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; | 371 | irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; |
366 | irq_mask_addr[0] += PERF_IRQMASK_6338_REG; | 372 | irq_mask_addr[0] += PERF_IRQMASK_6338_REG; |
373 | irq_stat_addr[1] = 0; | ||
374 | irq_mask_addr[1] = 0; | ||
367 | irq_bits = 32; | 375 | irq_bits = 32; |
368 | ext_irq_count = 4; | 376 | ext_irq_count = 4; |
369 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; | 377 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; |
@@ -371,6 +379,8 @@ static void bcm63xx_init_irq(void) | |||
371 | case BCM6345_CPU_ID: | 379 | case BCM6345_CPU_ID: |
372 | irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; | 380 | irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; |
373 | irq_mask_addr[0] += PERF_IRQMASK_6345_REG; | 381 | irq_mask_addr[0] += PERF_IRQMASK_6345_REG; |
382 | irq_stat_addr[1] = 0; | ||
383 | irq_mask_addr[1] = 0; | ||
374 | irq_bits = 32; | 384 | irq_bits = 32; |
375 | ext_irq_count = 4; | 385 | ext_irq_count = 4; |
376 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; | 386 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; |
@@ -378,6 +388,8 @@ static void bcm63xx_init_irq(void) | |||
378 | case BCM6348_CPU_ID: | 388 | case BCM6348_CPU_ID: |
379 | irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; | 389 | irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; |
380 | irq_mask_addr[0] += PERF_IRQMASK_6348_REG; | 390 | irq_mask_addr[0] += PERF_IRQMASK_6348_REG; |
391 | irq_stat_addr[1] = 0; | ||
392 | irq_mask_addr[1] = 0; | ||
381 | irq_bits = 32; | 393 | irq_bits = 32; |
382 | ext_irq_count = 4; | 394 | ext_irq_count = 4; |
383 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; | 395 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; |
@@ -385,6 +397,8 @@ static void bcm63xx_init_irq(void) | |||
385 | case BCM6358_CPU_ID: | 397 | case BCM6358_CPU_ID: |
386 | irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); | 398 | irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); |
387 | irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); | 399 | irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); |
400 | irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); | ||
401 | irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); | ||
388 | irq_bits = 32; | 402 | irq_bits = 32; |
389 | ext_irq_count = 4; | 403 | ext_irq_count = 4; |
390 | is_ext_irq_cascaded = 1; | 404 | is_ext_irq_cascaded = 1; |
@@ -395,6 +409,8 @@ static void bcm63xx_init_irq(void) | |||
395 | case BCM6362_CPU_ID: | 409 | case BCM6362_CPU_ID: |
396 | irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); | 410 | irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); |
397 | irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); | 411 | irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); |
412 | irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); | ||
413 | irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); | ||
398 | irq_bits = 64; | 414 | irq_bits = 64; |
399 | ext_irq_count = 4; | 415 | ext_irq_count = 4; |
400 | is_ext_irq_cascaded = 1; | 416 | is_ext_irq_cascaded = 1; |
@@ -405,6 +421,8 @@ static void bcm63xx_init_irq(void) | |||
405 | case BCM6368_CPU_ID: | 421 | case BCM6368_CPU_ID: |
406 | irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); | 422 | irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); |
407 | irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); | 423 | irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); |
424 | irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); | ||
425 | irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); | ||
408 | irq_bits = 64; | 426 | irq_bits = 64; |
409 | ext_irq_count = 6; | 427 | ext_irq_count = 6; |
410 | is_ext_irq_cascaded = 1; | 428 | is_ext_irq_cascaded = 1; |