Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits)
  MIPS: Delete unused function add_temporary_entry.
  MIPS: Set default pci cache line size.
  MIPS: Flush huge TLB
  MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM.
  MIPS: Octeon: Add support for OCTEON II PCIe
  MIPS: Octeon: Update PCI Latency timer and enable more error reporting.
  MIPS: Alchemy: Update cpu-feature-overrides
  MIPS: Alchemy: db1200: Improve PB1200 detection.
  MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code.
  MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller
  MIPS: Alchemy: irq: register pm at irq init time
  MIPS: Alchemy: Touchscreen support on DB1100
  MIPS: Alchemy: Hook up IrDA on DB1000/DB1100
  net/irda: convert au1k_ir to platform driver.
  MIPS: Alchemy: remove unused board headers
  MTD: nand: make au1550nd.c a platform_driver
  MIPS: Netlogic: Mark Netlogic chips as SMT capable
  MIPS: Netlogic: Add support for XLP 3XX cores
  MIPS: Netlogic: Merge some of XLR/XLP wakup code
  MIPS: Netlogic: Add default XLP config.
  ...

Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c,
traps.c} and drivers/tty/serial/Makefile

1 files changed, 333 insertions, 70 deletions

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 162e11b4ed75..9a216a451d92 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,19 +19,187 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_irq.h>
 
+static void __dispatch_internal(void) __maybe_unused;
+static void __dispatch_internal_64(void) __maybe_unused;
+static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+
+#ifndef BCMCPU_RUNTIME_DETECT
+#ifdef CONFIG_BCM63XX_CPU_6338
+#define irq_stat_reg            PERF_IRQSTAT_6338_REG
+#define irq_mask_reg            PERF_IRQMASK_6338_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6338
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+#define irq_stat_reg            PERF_IRQSTAT_6345_REG
+#define irq_mask_reg            PERF_IRQMASK_6345_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           0
+#define ext_irq_cfg_reg1        0
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+#define irq_stat_reg            PERF_IRQSTAT_6348_REG
+#define irq_mask_reg            PERF_IRQMASK_6348_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6348
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+#define irq_stat_reg            PERF_IRQSTAT_6358_REG
+#define irq_mask_reg            PERF_IRQMASK_6358_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6358
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+#define irq_stat_reg            PERF_IRQSTAT_6368_REG
+#define irq_mask_reg            PERF_IRQMASK_6368_REG
+#define irq_bits                64
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           6
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6368
+#define ext_irq_cfg_reg2        PERF_EXTIRQ_CFG_REG2_6368
+#endif
+
+#if irq_bits == 32
+#define dispatch_internal                       __dispatch_internal
+#define internal_irq_mask                       __internal_irq_mask_32
+#define internal_irq_unmask                     __internal_irq_unmask_32
+#else
+#define dispatch_internal                       __dispatch_internal_64
+#define internal_irq_mask                       __internal_irq_mask_64
+#define internal_irq_unmask                     __internal_irq_unmask_64
+#endif
+
+#define irq_stat_addr   (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
+#define irq_mask_addr   (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
+
+static inline void bcm63xx_init_irq(void)
+{
+}
+#else /* ! BCMCPU_RUNTIME_DETECT */
+
+static u32 irq_stat_addr, irq_mask_addr;
+static void (*dispatch_internal)(void);
+static int is_ext_irq_cascaded;
+static unsigned int ext_irq_count;
+static unsigned int ext_irq_start, ext_irq_end;
+static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+static void (*internal_irq_mask)(unsigned int irq);
+static void (*internal_irq_unmask)(unsigned int irq);
+
+static void bcm63xx_init_irq(void)
+{
+        int irq_bits;
+
+        irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
+        irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6338_REG;
+                irq_mask_addr += PERF_IRQMASK_6338_REG;
+                irq_bits = 32;
+                break;
+        case BCM6345_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6345_REG;
+                irq_mask_addr += PERF_IRQMASK_6345_REG;
+                irq_bits = 32;
+                break;
+        case BCM6348_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6348_REG;
+                irq_mask_addr += PERF_IRQMASK_6348_REG;
+                irq_bits = 32;
+                ext_irq_count = 4;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
+                break;
+        case BCM6358_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6358_REG;
+                irq_mask_addr += PERF_IRQMASK_6358_REG;
+                irq_bits = 32;
+                ext_irq_count = 4;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
+                break;
+        case BCM6368_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6368_REG;
+                irq_mask_addr += PERF_IRQMASK_6368_REG;
+                irq_bits = 64;
+                ext_irq_count = 6;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
+                ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
+                break;
+        default:
+                BUG();
+        }
+
+        if (irq_bits == 32) {
+                dispatch_internal = __dispatch_internal;
+                internal_irq_mask = __internal_irq_mask_32;
+                internal_irq_unmask = __internal_irq_unmask_32;
+        } else {
+                dispatch_internal = __dispatch_internal_64;
+                internal_irq_mask = __internal_irq_mask_64;
+                internal_irq_unmask = __internal_irq_unmask_64;
+        }
+}
+#endif /* ! BCMCPU_RUNTIME_DETECT */
+
+static inline u32 get_ext_irq_perf_reg(int irq)
+{
+        if (irq < 4)
+                return ext_irq_cfg_reg1;
+        return ext_irq_cfg_reg2;
+}
+
+static inline void handle_internal(int intbit)
+{
+        if (is_ext_irq_cascaded &&
+            intbit >= ext_irq_start && intbit <= ext_irq_end)
+                do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
+        else
+                do_IRQ(intbit + IRQ_INTERNAL_BASE);
+}
+
 /*
  * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  * prioritize any interrupt relatively to another. the static counter
  * will resume the loop where it ended the last time we left this
  * function.
  */
-static void bcm63xx_irq_dispatch_internal(void)
+static void __dispatch_internal(void)
 {
         u32 pending;
         static int i;
 
-        pending = bcm_perf_readl(PERF_IRQMASK_REG) &
-                bcm_perf_readl(PERF_IRQSTAT_REG);
+        pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
 
         if (!pending)
                 return ;
@@ -41,7 +209,28 @@ static void bcm63xx_irq_dispatch_internal(void)
 
                 i = (i + 1) & 0x1f;
                 if (pending & (1 << to_call)) {
-                        do_IRQ(to_call + IRQ_INTERNAL_BASE);
+                        handle_internal(to_call);
+                        break;
+                }
+        }
+}
+
+static void __dispatch_internal_64(void)
+{
+        u64 pending;
+        static int i;
+
+        pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
+
+        if (!pending)
+                return ;
+
+        while (1) {
+                int to_call = i;
+
+                i = (i + 1) & 0x3f;
+                if (pending & (1ull << to_call)) {
+                        handle_internal(to_call);
                         break;
                 }
         }
@@ -60,15 +249,17 @@ asmlinkage void plat_irq_dispatch(void)
                 if (cause & CAUSEF_IP7)
                         do_IRQ(7);
                 if (cause & CAUSEF_IP2)
-                        bcm63xx_irq_dispatch_internal();
-                if (cause & CAUSEF_IP3)
-                        do_IRQ(IRQ_EXT_0);
-                if (cause & CAUSEF_IP4)
-                        do_IRQ(IRQ_EXT_1);
-                if (cause & CAUSEF_IP5)
-                        do_IRQ(IRQ_EXT_2);
-                if (cause & CAUSEF_IP6)
-                        do_IRQ(IRQ_EXT_3);
+                        dispatch_internal();
+                if (!is_ext_irq_cascaded) {
+                        if (cause & CAUSEF_IP3)
+                                do_IRQ(IRQ_EXT_0);
+                        if (cause & CAUSEF_IP4)
+                                do_IRQ(IRQ_EXT_1);
+                        if (cause & CAUSEF_IP5)
+                                do_IRQ(IRQ_EXT_2);
+                        if (cause & CAUSEF_IP6)
+                                do_IRQ(IRQ_EXT_3);
+                }
         } while (1);
 }
 
@@ -76,24 +267,50 @@ asmlinkage void plat_irq_dispatch(void)
  * internal IRQs operations: only mask/unmask on PERF irq mask
  * register.
  */
-static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
+static void __internal_irq_mask_32(unsigned int irq)
 {
-        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
         u32 mask;
 
-        mask = bcm_perf_readl(PERF_IRQMASK_REG);
+        mask = bcm_readl(irq_mask_addr);
         mask &= ~(1 << irq);
-        bcm_perf_writel(mask, PERF_IRQMASK_REG);
+        bcm_writel(mask, irq_mask_addr);
 }
 
-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+static void __internal_irq_mask_64(unsigned int irq)
+{
+        u64 mask;
+
+        mask = bcm_readq(irq_mask_addr);
+        mask &= ~(1ull << irq);
+        bcm_writeq(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_32(unsigned int irq)
 {
-        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
         u32 mask;
 
-        mask = bcm_perf_readl(PERF_IRQMASK_REG);
+        mask = bcm_readl(irq_mask_addr);
         mask |= (1 << irq);
-        bcm_perf_writel(mask, PERF_IRQMASK_REG);
+        bcm_writel(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_64(unsigned int irq)
+{
+        u64 mask;
+
+        mask = bcm_readq(irq_mask_addr);
+        mask |= (1ull << irq);
+        bcm_writeq(mask, irq_mask_addr);
+}
+
+static void bcm63xx_internal_irq_mask(struct irq_data *d)
+{
+        internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
+}
+
+static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+{
+        internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
 }
 
 /*
@@ -102,94 +319,131 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
  */
 static void bcm63xx_external_irq_mask(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg &= ~EXTIRQ_CFG_MASK(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+
+        if (BCMCPU_IS_6348())
+                reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
+        else
+                reg &= ~EXTIRQ_CFG_MASK(irq % 4);
+
+        bcm_perf_writel(reg, regaddr);
+        if (is_ext_irq_cascaded)
+                internal_irq_mask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_unmask(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg |= EXTIRQ_CFG_MASK(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+
+        if (BCMCPU_IS_6348())
+                reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
+        else
+                reg |= EXTIRQ_CFG_MASK(irq % 4);
+
+        bcm_perf_writel(reg, regaddr);
+
+        if (is_ext_irq_cascaded)
+                internal_irq_unmask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_clear(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg |= EXTIRQ_CFG_CLEAR(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
-}
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
 
-static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
-{
-        set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-        irq_enable_hazard();
-        bcm63xx_external_irq_unmask(d);
-        return 0;
-}
+        if (BCMCPU_IS_6348())
+                reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
+        else
+                reg |= EXTIRQ_CFG_CLEAR(irq % 4);
 
-static void bcm63xx_external_irq_shutdown(struct irq_data *d)
-{
-        bcm63xx_external_irq_mask(d);
-        clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-        irq_disable_hazard();
+        bcm_perf_writel(reg, regaddr);
 }
 
 static int bcm63xx_external_irq_set_type(struct irq_data *d,
                                          unsigned int flow_type)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
+        int levelsense, sense, bothedge;
 
         flow_type &= IRQ_TYPE_SENSE_MASK;
 
         if (flow_type == IRQ_TYPE_NONE)
                 flow_type = IRQ_TYPE_LEVEL_LOW;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+        levelsense = sense = bothedge = 0;
         switch (flow_type) {
         case IRQ_TYPE_EDGE_BOTH:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+                bothedge = 1;
                 break;
 
         case IRQ_TYPE_EDGE_RISING:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_SENSE(irq);
-                reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+                sense = 1;
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg &= ~EXTIRQ_CFG_SENSE(irq);
-                reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
-                reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_SENSE(irq);
+                levelsense = 1;
+                sense = 1;
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
-                reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-                reg &= ~EXTIRQ_CFG_SENSE(irq);
+                levelsense = 1;
                 break;
 
         default:
                 printk(KERN_ERR "bogus flow type combination given !\n");
                 return -EINVAL;
         }
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+        irq %= 4;
+
+        if (BCMCPU_IS_6348()) {
+                if (levelsense)
+                        reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
+                if (sense)
+                        reg |= EXTIRQ_CFG_SENSE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
+                if (bothedge)
+                        reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+        }
+
+        if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+                if (levelsense)
+                        reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+                if (sense)
+                        reg |= EXTIRQ_CFG_SENSE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_SENSE(irq);
+                if (bothedge)
+                        reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+        }
+
+        bcm_perf_writel(reg, regaddr);
 
         irqd_set_trigger_type(d, flow_type);
         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -208,9 +462,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
 
 static struct irq_chip bcm63xx_external_irq_chip = {
         .name           = "bcm63xx_epic",
-        .irq_startup    = bcm63xx_external_irq_startup,
-        .irq_shutdown   = bcm63xx_external_irq_shutdown,
-
         .irq_ack        = bcm63xx_external_irq_clear,
 
         .irq_mask       = bcm63xx_external_irq_mask,
@@ -225,18 +476,30 @@ static struct irqaction cpu_ip2_cascade_action = {
         .flags          = IRQF_NO_THREAD,
 };
 
+static struct irqaction cpu_ext_cascade_action = {
+        .handler        = no_action,
+        .name           = "cascade_extirq",
+        .flags          = IRQF_NO_THREAD,
+};
+
 void __init arch_init_irq(void)
 {
         int i;
 
+        bcm63xx_init_irq();
         mips_cpu_irq_init();
         for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
                 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
                                          handle_level_irq);
 
-        for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
+        for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
                 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
                                          handle_edge_irq);
 
-        setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
+        if (!is_ext_irq_cascaded) {
+                for (i = 3; i < 3 + ext_irq_count; ++i)
+                        setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
+        }
+
+        setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
 }