MIPS: BCM63XX: add support for BCM3368 Cable Modem

The Broadcom BCM3368 Cable Modem SoC is extremely similar to the
existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort
in the existing code base is required to get it supported. This patch adds
support for the following on-chip peripherals:

- two UARTS
- GPIO
- Ethernet
- SPI
- PCI
- NOR Flash

The most noticeable difference with 3368 is that it has its peripheral
register at 0xfff8_0000 we check that separately in ioremap.h. Since
3368 is identical to 6358 for its clock and reset bits, we use them
verbatim.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 25 insertions, 3 deletions

diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 79fe32df5e96..7e17374a9ae8 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
+static const unsigned long bcm3368_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(3368)
+};
+
+static const int bcm3368_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(3368)
+};
+
 static const unsigned long bcm6328_regs_base[] = {
         __GEN_CPU_REGS_TABLE(6328)
 };
@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void)
 static unsigned int detect_cpu_clock(void)
 {
         switch (bcm63xx_get_cpu_id()) {
+        case BCM3368_CPU_ID:
+                return 300000000;
+
         case BCM6328_CPU_ID:
         {
                 unsigned int tmp, mips_pll_fcvo;
@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void)
                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
         }
 
-        if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+        if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
                 val = bcm_memc_readl(MEMC_CFG_REG);
                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
                 chipid_reg = BCM_6345_PERF_BASE;
                 break;
         case CPU_BMIPS4350:
-                if ((read_c0_prid() & 0xf0) == 0x10)
+                switch ((read_c0_prid() & 0xff)) {
+                case 0x04:
+                        chipid_reg = BCM_3368_PERF_BASE;
+                        break;
+                case 0x10:
                         chipid_reg = BCM_6345_PERF_BASE;
-                else
+                        break;
+                default:
                         chipid_reg = BCM_6368_PERF_BASE;
+                        break;
+                }
                 break;
         }
 
@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 
         switch (bcm63xx_cpu_id) {
+        case BCM3368_CPU_ID:
+                bcm63xx_regs_base = bcm3368_regs_base;
+                bcm63xx_irqs = bcm3368_irqs;
+                break;
         case BCM6328_CPU_ID:
                 bcm63xx_regs_base = bcm6328_regs_base;
                 bcm63xx_irqs = bcm6328_irqs;