diff options
author | Hauke Mehrtens <hauke@hauke-m.de> | 2011-07-22 19:20:13 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-08-08 14:29:31 -0400 |
commit | a656ffcbc7a98a80d2136ae6bbdd8ae2eb48c78a (patch) | |
tree | 9b732b9a15ad8cc9c8790f36f3ac9a00bf6972c2 /arch/mips/bcm47xx | |
parent | 08ccf57283f89adbc2ff897ad82d6ad4560db7cd (diff) |
bcm47xx: make it possible to build bcm47xx without ssb.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'arch/mips/bcm47xx')
-rw-r--r-- | arch/mips/bcm47xx/Kconfig | 18 | ||||
-rw-r--r-- | arch/mips/bcm47xx/Makefile | 3 | ||||
-rw-r--r-- | arch/mips/bcm47xx/gpio.c | 6 | ||||
-rw-r--r-- | arch/mips/bcm47xx/nvram.c | 4 | ||||
-rw-r--r-- | arch/mips/bcm47xx/serial.c | 4 | ||||
-rw-r--r-- | arch/mips/bcm47xx/setup.c | 8 | ||||
-rw-r--r-- | arch/mips/bcm47xx/time.c | 2 |
7 files changed, 44 insertions, 1 deletions
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig new file mode 100644 index 000000000000..0346f92d12a2 --- /dev/null +++ b/arch/mips/bcm47xx/Kconfig | |||
@@ -0,0 +1,18 @@ | |||
1 | if BCM47XX | ||
2 | |||
3 | config BCM47XX_SSB | ||
4 | bool "SSB Support for Broadcom BCM47XX" | ||
5 | select SYS_HAS_CPU_MIPS32_R1 | ||
6 | select SSB | ||
7 | select SSB_DRIVER_MIPS | ||
8 | select SSB_DRIVER_EXTIF | ||
9 | select SSB_EMBEDDED | ||
10 | select SSB_B43_PCI_BRIDGE if PCI | ||
11 | select SSB_PCICORE_HOSTMODE if PCI | ||
12 | default y | ||
13 | help | ||
14 | Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. | ||
15 | |||
16 | This will generate an image with support for SSB and MIPS32 R1 instruction set. | ||
17 | |||
18 | endif | ||
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index 7465e8a72d9a..4add17349ff9 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile | |||
@@ -3,4 +3,5 @@ | |||
3 | # under Linux. | 3 | # under Linux. |
4 | # | 4 | # |
5 | 5 | ||
6 | obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o | 6 | obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o |
7 | obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o | ||
diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c index 99e1c50caf6b..2b804c36750b 100644 --- a/arch/mips/bcm47xx/gpio.c +++ b/arch/mips/bcm47xx/gpio.c | |||
@@ -21,6 +21,7 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); | |||
21 | int gpio_request(unsigned gpio, const char *tag) | 21 | int gpio_request(unsigned gpio, const char *tag) |
22 | { | 22 | { |
23 | switch (bcm47xx_bus_type) { | 23 | switch (bcm47xx_bus_type) { |
24 | #ifdef CONFIG_BCM47XX_SSB | ||
24 | case BCM47XX_BUS_TYPE_SSB: | 25 | case BCM47XX_BUS_TYPE_SSB: |
25 | if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && | 26 | if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && |
26 | ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) | 27 | ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) |
@@ -34,6 +35,7 @@ int gpio_request(unsigned gpio, const char *tag) | |||
34 | return -EBUSY; | 35 | return -EBUSY; |
35 | 36 | ||
36 | return 0; | 37 | return 0; |
38 | #endif | ||
37 | } | 39 | } |
38 | return -EINVAL; | 40 | return -EINVAL; |
39 | } | 41 | } |
@@ -42,6 +44,7 @@ EXPORT_SYMBOL(gpio_request); | |||
42 | void gpio_free(unsigned gpio) | 44 | void gpio_free(unsigned gpio) |
43 | { | 45 | { |
44 | switch (bcm47xx_bus_type) { | 46 | switch (bcm47xx_bus_type) { |
47 | #ifdef CONFIG_BCM47XX_SSB | ||
45 | case BCM47XX_BUS_TYPE_SSB: | 48 | case BCM47XX_BUS_TYPE_SSB: |
46 | if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && | 49 | if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && |
47 | ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) | 50 | ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) |
@@ -53,6 +56,7 @@ void gpio_free(unsigned gpio) | |||
53 | 56 | ||
54 | clear_bit(gpio, gpio_in_use); | 57 | clear_bit(gpio, gpio_in_use); |
55 | return; | 58 | return; |
59 | #endif | ||
56 | } | 60 | } |
57 | } | 61 | } |
58 | EXPORT_SYMBOL(gpio_free); | 62 | EXPORT_SYMBOL(gpio_free); |
@@ -60,6 +64,7 @@ EXPORT_SYMBOL(gpio_free); | |||
60 | int gpio_to_irq(unsigned gpio) | 64 | int gpio_to_irq(unsigned gpio) |
61 | { | 65 | { |
62 | switch (bcm47xx_bus_type) { | 66 | switch (bcm47xx_bus_type) { |
67 | #ifdef CONFIG_BCM47XX_SSB | ||
63 | case BCM47XX_BUS_TYPE_SSB: | 68 | case BCM47XX_BUS_TYPE_SSB: |
64 | if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) | 69 | if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) |
65 | return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; | 70 | return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; |
@@ -67,6 +72,7 @@ int gpio_to_irq(unsigned gpio) | |||
67 | return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; | 72 | return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; |
68 | else | 73 | else |
69 | return -EINVAL; | 74 | return -EINVAL; |
75 | #endif | ||
70 | } | 76 | } |
71 | return -EINVAL; | 77 | return -EINVAL; |
72 | } | 78 | } |
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index bcac2ffd1248..4e994edb1425 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c | |||
@@ -26,7 +26,9 @@ static char nvram_buf[NVRAM_SPACE]; | |||
26 | /* Probe for NVRAM header */ | 26 | /* Probe for NVRAM header */ |
27 | static void early_nvram_init(void) | 27 | static void early_nvram_init(void) |
28 | { | 28 | { |
29 | #ifdef CONFIG_BCM47XX_SSB | ||
29 | struct ssb_mipscore *mcore_ssb; | 30 | struct ssb_mipscore *mcore_ssb; |
31 | #endif | ||
30 | struct nvram_header *header; | 32 | struct nvram_header *header; |
31 | int i; | 33 | int i; |
32 | u32 base = 0; | 34 | u32 base = 0; |
@@ -35,11 +37,13 @@ static void early_nvram_init(void) | |||
35 | u32 *src, *dst; | 37 | u32 *src, *dst; |
36 | 38 | ||
37 | switch (bcm47xx_bus_type) { | 39 | switch (bcm47xx_bus_type) { |
40 | #ifdef CONFIG_BCM47XX_SSB | ||
38 | case BCM47XX_BUS_TYPE_SSB: | 41 | case BCM47XX_BUS_TYPE_SSB: |
39 | mcore_ssb = &bcm47xx_bus.ssb.mipscore; | 42 | mcore_ssb = &bcm47xx_bus.ssb.mipscore; |
40 | base = mcore_ssb->flash_window; | 43 | base = mcore_ssb->flash_window; |
41 | lim = mcore_ssb->flash_window_size; | 44 | lim = mcore_ssb->flash_window_size; |
42 | break; | 45 | break; |
46 | #endif | ||
43 | } | 47 | } |
44 | 48 | ||
45 | off = FLASH_MIN; | 49 | off = FLASH_MIN; |
diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c index 17c67e24b549..fcef68836979 100644 --- a/arch/mips/bcm47xx/serial.c +++ b/arch/mips/bcm47xx/serial.c | |||
@@ -23,6 +23,7 @@ static struct platform_device uart8250_device = { | |||
23 | }, | 23 | }, |
24 | }; | 24 | }; |
25 | 25 | ||
26 | #ifdef CONFIG_BCM47XX_SSB | ||
26 | static int __init uart8250_init_ssb(void) | 27 | static int __init uart8250_init_ssb(void) |
27 | { | 28 | { |
28 | int i; | 29 | int i; |
@@ -44,12 +45,15 @@ static int __init uart8250_init_ssb(void) | |||
44 | } | 45 | } |
45 | return platform_device_register(&uart8250_device); | 46 | return platform_device_register(&uart8250_device); |
46 | } | 47 | } |
48 | #endif | ||
47 | 49 | ||
48 | static int __init uart8250_init(void) | 50 | static int __init uart8250_init(void) |
49 | { | 51 | { |
50 | switch (bcm47xx_bus_type) { | 52 | switch (bcm47xx_bus_type) { |
53 | #ifdef CONFIG_BCM47XX_SSB | ||
51 | case BCM47XX_BUS_TYPE_SSB: | 54 | case BCM47XX_BUS_TYPE_SSB: |
52 | return uart8250_init_ssb(); | 55 | return uart8250_init_ssb(); |
56 | #endif | ||
53 | } | 57 | } |
54 | return -EINVAL; | 58 | return -EINVAL; |
55 | } | 59 | } |
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 271cedb339ae..142cf1bc8884 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c | |||
@@ -47,9 +47,11 @@ static void bcm47xx_machine_restart(char *command) | |||
47 | local_irq_disable(); | 47 | local_irq_disable(); |
48 | /* Set the watchdog timer to reset immediately */ | 48 | /* Set the watchdog timer to reset immediately */ |
49 | switch (bcm47xx_bus_type) { | 49 | switch (bcm47xx_bus_type) { |
50 | #ifdef CONFIG_BCM47XX_SSB | ||
50 | case BCM47XX_BUS_TYPE_SSB: | 51 | case BCM47XX_BUS_TYPE_SSB: |
51 | ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1); | 52 | ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1); |
52 | break; | 53 | break; |
54 | #endif | ||
53 | } | 55 | } |
54 | while (1) | 56 | while (1) |
55 | cpu_relax(); | 57 | cpu_relax(); |
@@ -60,14 +62,17 @@ static void bcm47xx_machine_halt(void) | |||
60 | /* Disable interrupts and watchdog and spin forever */ | 62 | /* Disable interrupts and watchdog and spin forever */ |
61 | local_irq_disable(); | 63 | local_irq_disable(); |
62 | switch (bcm47xx_bus_type) { | 64 | switch (bcm47xx_bus_type) { |
65 | #ifdef CONFIG_BCM47XX_SSB | ||
63 | case BCM47XX_BUS_TYPE_SSB: | 66 | case BCM47XX_BUS_TYPE_SSB: |
64 | ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); | 67 | ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); |
65 | break; | 68 | break; |
69 | #endif | ||
66 | } | 70 | } |
67 | while (1) | 71 | while (1) |
68 | cpu_relax(); | 72 | cpu_relax(); |
69 | } | 73 | } |
70 | 74 | ||
75 | #ifdef CONFIG_BCM47XX_SSB | ||
71 | #define READ_FROM_NVRAM(_outvar, name, buf) \ | 76 | #define READ_FROM_NVRAM(_outvar, name, buf) \ |
72 | if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ | 77 | if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ |
73 | sprom->_outvar = simple_strtoul(buf, NULL, 0); | 78 | sprom->_outvar = simple_strtoul(buf, NULL, 0); |
@@ -288,13 +293,16 @@ static void __init bcm47xx_register_ssb(void) | |||
288 | } | 293 | } |
289 | } | 294 | } |
290 | } | 295 | } |
296 | #endif | ||
291 | 297 | ||
292 | void __init plat_mem_setup(void) | 298 | void __init plat_mem_setup(void) |
293 | { | 299 | { |
294 | struct cpuinfo_mips *c = ¤t_cpu_data; | 300 | struct cpuinfo_mips *c = ¤t_cpu_data; |
295 | 301 | ||
302 | #ifdef CONFIG_BCM47XX_SSB | ||
296 | bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; | 303 | bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; |
297 | bcm47xx_register_ssb(); | 304 | bcm47xx_register_ssb(); |
305 | #endif | ||
298 | 306 | ||
299 | _machine_restart = bcm47xx_machine_restart; | 307 | _machine_restart = bcm47xx_machine_restart; |
300 | _machine_halt = bcm47xx_machine_halt; | 308 | _machine_halt = bcm47xx_machine_halt; |
diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 50aea2e1808c..03dfc65b1b60 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c | |||
@@ -40,9 +40,11 @@ void __init plat_time_init(void) | |||
40 | write_c0_compare(0xffff); | 40 | write_c0_compare(0xffff); |
41 | 41 | ||
42 | switch (bcm47xx_bus_type) { | 42 | switch (bcm47xx_bus_type) { |
43 | #ifdef CONFIG_BCM47XX_SSB | ||
43 | case BCM47XX_BUS_TYPE_SSB: | 44 | case BCM47XX_BUS_TYPE_SSB: |
44 | hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; | 45 | hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; |
45 | break; | 46 | break; |
47 | #endif | ||
46 | } | 48 | } |
47 | 49 | ||
48 | if (!hz) | 50 | if (!hz) |