diff options
author | Sergei Shtylylov <sshtylyov@ru.mvista.com> | 2006-01-25 13:27:10 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-02-07 08:30:23 -0500 |
commit | 80730555af2ef1932bd8b9943333e8837dddfacc (patch) | |
tree | 881772d4c6d1b59bc7d3d101dad9465a2af1c682 /arch/mips/au1000 | |
parent | 6fe2a5681fff0cbeaf9a2d3778661be62a7f2f06 (diff) |
[MIPS] Au1xx0: really set KSEG0 to uncached on reboot
Fix a really old buglet in AMD Au1xx0 restart code: instead of
modifying the whole CP0 Config.K0 field to 010b (meaning KSEG0 uncached)
before flushing the caches and resetting a board, it only sets bit 1 of that
reg. which is effectively a NOP since Config.K0 == 011b as the kernel sets it
up (which is also its default value for Au1xx0).
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000')
-rw-r--r-- | arch/mips/au1000/common/reset.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c index 65b84db800e4..4ffccedf5967 100644 --- a/arch/mips/au1000/common/reset.c +++ b/arch/mips/au1000/common/reset.c | |||
@@ -151,7 +151,7 @@ void au1000_restart(char *command) | |||
151 | } | 151 | } |
152 | 152 | ||
153 | set_c0_status(ST0_BEV | ST0_ERL); | 153 | set_c0_status(ST0_BEV | ST0_ERL); |
154 | set_c0_config(CONF_CM_UNCACHED); | 154 | change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); |
155 | flush_cache_all(); | 155 | flush_cache_all(); |
156 | write_c0_wired(0); | 156 | write_c0_wired(0); |
157 | 157 | ||