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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:09 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:09 -0400
commit91a2fcc88634663e9e13dcdfad0e4a860e64aeee (patch)
treea86b936f1057207d46e5a07ed826052ff640869a /arch/mips/au1000
parent90b02340dcc6ce00bf22c48f4865915f5989e5e4 (diff)
[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000')
-rw-r--r--arch/mips/au1000/common/irq.c4
-rw-r--r--arch/mips/au1000/common/time.c40
2 files changed, 1 insertions, 43 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index db2ba0dbfd5a..47949d6f2c10 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -65,8 +65,6 @@
65#define EXT_INTC1_REQ1 5 /* IP 5 */ 65#define EXT_INTC1_REQ1 5 /* IP 5 */
66#define MIPS_TIMER_IP 7 /* IP 7 */ 66#define MIPS_TIMER_IP 7 /* IP 7 */
67 67
68extern void mips_timer_interrupt(void);
69
70void (*board_init_irq)(void); 68void (*board_init_irq)(void);
71 69
72static DEFINE_SPINLOCK(irq_lock); 70static DEFINE_SPINLOCK(irq_lock);
@@ -635,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void)
635 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 633 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
636 634
637 if (pending & CAUSEF_IP7) 635 if (pending & CAUSEF_IP7)
638 mips_timer_interrupt(); 636 ll_timer_interrupt(63);
639 else if (pending & CAUSEF_IP2) 637 else if (pending & CAUSEF_IP2)
640 intc0_req0_irqdispatch(); 638 intc0_req0_irqdispatch();
641 else if (pending & CAUSEF_IP3) 639 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index fb1fd50f19a6..726c340460b6 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -64,48 +64,8 @@ static unsigned long last_pc0, last_match20;
64 64
65static DEFINE_SPINLOCK(time_lock); 65static DEFINE_SPINLOCK(time_lock);
66 66
67static inline void ack_r4ktimer(unsigned long newval)
68{
69 write_c0_compare(newval);
70}
71
72/*
73 * There are a lot of conceptually broken versions of the MIPS timer interrupt
74 * handler floating around. This one is rather different, but the algorithm
75 * is provably more robust.
76 */
77unsigned long wtimer; 67unsigned long wtimer;
78 68
79void mips_timer_interrupt(void)
80{
81 int irq = 63;
82
83 irq_enter();
84 kstat_this_cpu.irqs[irq]++;
85
86 if (r4k_offset == 0)
87 goto null;
88
89 do {
90 kstat_this_cpu.irqs[irq]++;
91 do_timer(1);
92#ifndef CONFIG_SMP
93 update_process_times(user_mode(get_irq_regs()));
94#endif
95 r4k_cur += r4k_offset;
96 ack_r4ktimer(r4k_cur);
97
98 } while (((unsigned long)read_c0_count()
99 - r4k_cur) < 0x7fffffff);
100
101 irq_exit();
102 return;
103
104null:
105 ack_r4ktimer(0);
106 irq_exit();
107}
108
109#ifdef CONFIG_PM 69#ifdef CONFIG_PM
110irqreturn_t counter0_irq(int irq, void *dev_id) 70irqreturn_t counter0_irq(int irq, void *dev_id)
111{ 71{