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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-05-26 11:44:54 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-05 19:15:13 -0400
commit9370b35175ca43fad7d24bc7b391473f3becbee8 (patch)
tree4d1f3e7a0708c86da26720288711f8702b00b601 /arch/mips/au1000
parentcac4bcbce0e800f2219a27b66aaeb4a33f2e3dbc (diff)
[MIPS] Save write-only Config.OD from being clobbered
Save the Config.OD bit from being clobbered by coherency_setup(). This bit, when set, fixes various errata in the early steppings of Au1x00 SOCs. Unfortunately, the bit was write-only on the most early of them. In addition, also restore the bit after a wakeup from sleep. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000')
-rw-r--r--arch/mips/au1000/common/sleeper.S5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/au1000/common/sleeper.S
index 44dac3b0df3b..683d9da84b66 100644
--- a/arch/mips/au1000/common/sleeper.S
+++ b/arch/mips/au1000/common/sleeper.S
@@ -112,6 +112,11 @@ sdsleep:
112 mtc0 k0, CP0_PAGEMASK 112 mtc0 k0, CP0_PAGEMASK
113 lw k0, 0x14(sp) 113 lw k0, 0x14(sp)
114 mtc0 k0, CP0_CONFIG 114 mtc0 k0, CP0_CONFIG
115
116 /* We need to catch the ealry Alchemy SOCs with
117 * the write-only Config[OD] bit and set it back to one...
118 */
119 jal au1x00_fixup_config_od
115 lw $1, PT_R1(sp) 120 lw $1, PT_R1(sp)
116 lw $2, PT_R2(sp) 121 lw $2, PT_R2(sp)
117 lw $3, PT_R3(sp) 122 lw $3, PT_R3(sp)