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authorPete Popov <ppopov@embeddedalley.com>2005-03-01 01:33:16 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:47 -0400
commite3ad1c23ba72214669b364c6fa304531dc768c3e (patch)
treebc1e0004d3df66b4c37a2deb8d89431657039719 /arch/mips/au1000/pb1200
parent784f7b9d895893c6aa3ca471c1344a62fc29c285 (diff)
Base Au1200 2.6 support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000/pb1200')
-rw-r--r--arch/mips/au1000/pb1200/Makefile5
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c187
-rw-r--r--arch/mips/au1000/pb1200/init.c69
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c180
4 files changed, 441 insertions, 0 deletions
diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile
new file mode 100644
index 000000000000..22b673cf55af
--- /dev/null
+++ b/arch/mips/au1000/pb1200/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Alchemy Semiconductor PB1200 board.
3#
4
5lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
new file mode 100644
index 000000000000..209a07cb7321
--- /dev/null
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -0,0 +1,187 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/sched.h>
29#include <linux/ioport.h>
30#include <linux/mm.h>
31#include <linux/console.h>
32#include <linux/mc146818rtc.h>
33#include <linux/delay.h>
34
35#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
36#include <linux/ide.h>
37#endif
38
39#include <asm/cpu.h>
40#include <asm/bootinfo.h>
41#include <asm/irq.h>
42#include <asm/mipsregs.h>
43#include <asm/reboot.h>
44#include <asm/pgtable.h>
45#include <asm/mach-au1x00/au1000.h>
46#include <asm/mach-au1x00/au1xxx_dbdma.h>
47
48#ifdef CONFIG_MIPS_PB1200
49#include <asm/mach-pb1x00/pb1200.h>
50#endif
51
52#ifdef CONFIG_MIPS_DB1200
53#include <asm/mach-db1x00/db1200.h>
54#define PB1200_ETH_INT DB1200_ETH_INT
55#define PB1200_IDE_INT DB1200_IDE_INT
56#endif
57
58extern void _board_init_irq(void);
59extern void (*board_init_irq)(void);
60
61#ifdef CONFIG_BLK_DEV_IDE_AU1XXX
62extern struct ide_ops *ide_ops;
63extern struct ide_ops au1xxx_ide_ops;
64extern u32 au1xxx_ide_virtbase;
65extern u64 au1xxx_ide_physbase;
66extern int au1xxx_ide_irq;
67
68u32 led_base_addr;
69/* Ddma */
70chan_tab_t *ide_read_ch, *ide_write_ch;
71u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
72
73dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 };
74#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
75
76void board_reset (void)
77{
78 bcsr->resets = 0;
79}
80
81void __init board_setup(void)
82{
83 char *argptr = NULL;
84 u32 pin_func;
85
86#if 0
87 /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
88 * but it is board specific code, so put it here.
89 */
90 pin_func = au_readl(SYS_PINFUNC);
91 au_sync();
92 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
93 au_writel(pin_func, SYS_PINFUNC);
94
95 au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
96 au_sync();
97#endif
98
99#if defined( CONFIG_I2C_ALGO_AU1550 )
100 {
101 u32 freq0, clksrc;
102
103 /* Select SMBUS in CPLD */
104 bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
105
106 pin_func = au_readl(SYS_PINFUNC);
107 au_sync();
108 pin_func &= ~(3<<17 | 1<<4);
109 /* Set GPIOs correctly */
110 pin_func |= 2<<17;
111 au_writel(pin_func, SYS_PINFUNC);
112 au_sync();
113
114 /* The i2c driver depends on 50Mhz clock */
115 freq0 = au_readl(SYS_FREQCTRL0);
116 au_sync();
117 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
118 freq0 |= (3<<SYS_FC_FRDIV1_BIT);
119 /* 396Mhz / (3+1)*2 == 49.5Mhz */
120 au_writel(freq0, SYS_FREQCTRL0);
121 au_sync();
122 freq0 |= SYS_FC_FE1;
123 au_writel(freq0, SYS_FREQCTRL0);
124 au_sync();
125
126 clksrc = au_readl(SYS_CLKSRC);
127 au_sync();
128 clksrc &= ~0x01f00000;
129 /* bit 22 is EXTCLK0 for PSC0 */
130 clksrc |= (0x3 << 22);
131 au_writel(clksrc, SYS_CLKSRC);
132 au_sync();
133 }
134#endif
135
136#ifdef CONFIG_FB_AU1200
137 argptr = prom_getcmdline();
138#ifdef CONFIG_MIPS_PB1200
139 strcat(argptr, " video=au1200fb:panel:s11");
140#endif
141#ifdef CONFIG_MIPS_DB1200
142 strcat(argptr, " video=au1200fb:panel:s7");
143#endif
144#endif
145
146#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
147 /*
148 * Iniz IDE parameters
149 */
150 ide_ops = &au1xxx_ide_ops;
151 au1xxx_ide_irq = PB1200_IDE_INT;
152 au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
153 au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
154 /*
155 * change PIO or PIO+Ddma
156 * check the GPIO-5 pin condition. pb1200:s18_dot */
157 switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0;
158#endif
159
160 /* The Pb1200 development board uses external MUX for PSC0 to
161 support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
162 */
163#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
164 #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
165 Refer to Pb1200/Db1200 documentation.
166#elif defined( CONFIG_AU1550_PSC_SPI )
167 bcsr->resets |= BCSR_RESETS_PCS0MUX;
168#elif defined( CONFIG_I2C_ALGO_AU1550 )
169 bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
170#endif
171 au_sync();
172
173#ifdef CONFIG_MIPS_PB1200
174 printk("AMD Alchemy Pb1200 Board\n");
175#endif
176#ifdef CONFIG_MIPS_DB1200
177 printk("AMD Alchemy Db1200 Board\n");
178#endif
179#if 0
180 /* Setup Pb1200 External Interrupt Controller */
181 {
182 extern void (*board_init_irq)(void);
183 extern void _board_init_irq(void);
184 board_init_irq = _board_init_irq;
185 }
186#endif
187}
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
new file mode 100644
index 000000000000..27f09e374e15
--- /dev/null
+++ b/arch/mips/au1000/pb1200/init.c
@@ -0,0 +1,69 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PB1200 board setup
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/init.h>
31#include <linux/mm.h>
32#include <linux/sched.h>
33#include <linux/bootmem.h>
34#include <asm/addrspace.h>
35#include <asm/bootinfo.h>
36#include <linux/string.h>
37#include <linux/kernel.h>
38
39int prom_argc;
40char **prom_argv, **prom_envp;
41extern void __init prom_init_cmdline(void);
42extern char *prom_getenv(char *envname);
43
44const char *get_system_type(void)
45{
46 return "Alchemy Pb1200";
47}
48
49void __init prom_init(void)
50{
51 unsigned char *memsize_str;
52 unsigned long memsize;
53
54 prom_argc = (int) fw_arg0;
55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2;
57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1200;
60
61 prom_init_cmdline();
62 memsize_str = prom_getenv("memsize");
63 if (!memsize_str) {
64 memsize = 0x08000000;
65 } else {
66 memsize = simple_strtol(memsize_str, NULL, 0);
67 }
68 add_memory_region(0, memsize, BOOT_MEM_RAM);
69}
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
new file mode 100644
index 000000000000..2ec64e78aa01
--- /dev/null
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -0,0 +1,180 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#include <linux/errno.h>
26#include <linux/init.h>
27#include <linux/irq.h>
28#include <linux/kernel_stat.h>
29#include <linux/module.h>
30#include <linux/signal.h>
31#include <linux/sched.h>
32#include <linux/types.h>
33#include <linux/interrupt.h>
34#include <linux/ioport.h>
35#include <linux/timex.h>
36#include <linux/slab.h>
37#include <linux/random.h>
38#include <linux/delay.h>
39
40#include <asm/bitops.h>
41#include <asm/bootinfo.h>
42#include <asm/io.h>
43#include <asm/mipsregs.h>
44#include <asm/system.h>
45#include <asm/mach-au1x00/au1000.h>
46
47#ifdef CONFIG_MIPS_PB1200
48#include <asm/mach-pb1x00/pb1200.h>
49#endif
50
51#ifdef CONFIG_MIPS_DB1200
52#include <asm/mach-db1x00/db1200.h>
53#define PB1200_INT_BEGIN DB1200_INT_BEGIN
54#define PB1200_INT_END DB1200_INT_END
55#endif
56
57au1xxx_irq_map_t au1xxx_irq_map[] = {
58 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
59};
60
61int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
62
63/*
64 * Support for External interrupts on the PbAu1200 Development platform.
65 */
66static volatile int pb1200_cascade_en=0;
67
68void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
69{
70 unsigned short bisr = bcsr->int_status;
71 int extirq_nr = 0;
72
73 /* Clear all the edge interrupts. This has no effect on level */
74 bcsr->int_status = bisr;
75 for( ; bisr; bisr &= (bisr-1) )
76 {
77 extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
78 /* Ack and dispatch IRQ */
79 do_IRQ(extirq_nr,regs);
80 }
81}
82
83inline void pb1200_enable_irq(unsigned int irq_nr)
84{
85 bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
86 bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
87}
88
89inline void pb1200_disable_irq(unsigned int irq_nr)
90{
91 bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
92 bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
93}
94
95static unsigned int pb1200_startup_irq( unsigned int irq_nr )
96{
97 if (++pb1200_cascade_en == 1)
98 {
99 request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
100 0, "Pb1200 Cascade", &pb1200_cascade_handler );
101#ifdef CONFIG_MIPS_PB1200
102 /* We have a problem with CPLD rev3. Enable a workaround */
103 if( ((bcsr->whoami & BCSR_WHOAMI_CPLD)>>4) <= 3)
104 {
105 printk("\nWARNING!!!\n");
106 printk("\nWARNING!!!\n");
107 printk("\nWARNING!!!\n");
108 printk("\nWARNING!!!\n");
109 printk("\nWARNING!!!\n");
110 printk("\nWARNING!!!\n");
111 printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
112 printk("updated to latest revision. This software will not\n");
113 printk("work on anything less than CPLD rev4\n");
114 printk("\nWARNING!!!\n");
115 printk("\nWARNING!!!\n");
116 printk("\nWARNING!!!\n");
117 printk("\nWARNING!!!\n");
118 printk("\nWARNING!!!\n");
119 printk("\nWARNING!!!\n");
120 while(1);
121 }
122#endif
123 }
124 pb1200_enable_irq(irq_nr);
125 return 0;
126}
127
128static void pb1200_shutdown_irq( unsigned int irq_nr )
129{
130 pb1200_disable_irq(irq_nr);
131 if (--pb1200_cascade_en == 0)
132 {
133 free_irq(AU1000_GPIO_7,&pb1200_cascade_handler );
134 }
135 return;
136}
137
138static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr)
139{
140 pb1200_disable_irq( irq_nr );
141}
142
143static void pb1200_end_irq(unsigned int irq_nr)
144{
145 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
146 pb1200_enable_irq(irq_nr);
147 }
148}
149
150static struct hw_interrupt_type external_irq_type =
151{
152#ifdef CONFIG_MIPS_PB1200
153 "Pb1200 Ext",
154#endif
155#ifdef CONFIG_MIPS_DB1200
156 "Db1200 Ext",
157#endif
158 pb1200_startup_irq,
159 pb1200_shutdown_irq,
160 pb1200_enable_irq,
161 pb1200_disable_irq,
162 pb1200_mask_and_ack_irq,
163 pb1200_end_irq,
164 NULL
165};
166
167void _board_init_irq(void)
168{
169 int irq_nr;
170
171 for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
172 {
173 irq_desc[irq_nr].handler = &external_irq_type;
174 pb1200_disable_irq(irq_nr);
175 }
176
177 /* GPIO_7 can not be hooked here, so it is hooked upon first
178 request of any source attached to the cascade */
179}
180
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