[MIPS] Alchemy: don't unmask timer IRQ early

Defer the unmasking of the count/compare interrupt (IRQ5) till the
clockevent driver initialization:

- only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the
  ALLINTS macro -- this change is blessed by AMD as I saw it in their own
  patch; :-)

- do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's
  no 32 KHz crystal.

Update the copyrights (taking into account my prior changes), also removing
Pete Popov's old email...

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 6 deletions

diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index e122bbc6cd88..1966964590ab 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
+ * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
  * Copied and modified Carsten Langgaard's time.c
  *
  * Carsten Langgaard, carstenl@mips.com
@@ -265,12 +265,8 @@ void __init plat_time_init(void)
          * Check to ensure we really have a 32KHz oscillator before
          * we do this.
          */
-        if (no_au1xxx_32khz) {
+        if (no_au1xxx_32khz)
                 printk("WARNING: no 32KHz clock found.\n");
-
-                /* Ensure we get CPO_COUNTER interrupts.  */
-                set_c0_status(IE_IRQ5);
-        }
         else {
                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
                 au_writel(0, SYS_TOYWRITE);