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authorFlorian Fainelli <florian.fainelli@telecomint.eu>2007-05-22 15:44:42 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 12:32:56 -0400
commit4ead16819b4c61fea9bb73eb470f6bb1d3350e5c (patch)
treea001b0f2d2893ee6e266b00da27cd02ccef1f671 /arch/mips/au1000/common/gpio.c
parent82b8d2250c4b606e190853db9505b54b9fb71aa5 (diff)
[MIPS] Add generic GPIO to Au1x00
This patch adds support for the generic GPIO API to Au1x00 boards. It requires the generic GPIO patch for MIPS boards by Yoichi Yuasa. Now there is a MIPS target using it, can you queue these patchset for 2.6.22 ? Thank you very much in advance. Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000/common/gpio.c')
-rw-r--r--arch/mips/au1000/common/gpio.c124
1 files changed, 81 insertions, 43 deletions
diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c
index ce55297dcb8c..7abe42099439 100644
--- a/arch/mips/au1000/common/gpio.c
+++ b/arch/mips/au1000/common/gpio.c
@@ -1,4 +1,7 @@
1/* 1/*
2 * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * Architecture specific GPIO support
4 *
2 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
@@ -18,101 +21,136 @@
18 * You should have received a copy of the GNU General Public License along 21 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc., 22 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO line : GPIO1
27 * others have a second one : GPIO2
21 */ 28 */
29
30#include <linux/autoconf.h>
31#include <linux/init.h>
32#include <linux/io.h>
33#include <linux/types.h>
22#include <linux/module.h> 34#include <linux/module.h>
23#include <au1000.h> 35
24#include <au1xxx_gpio.h> 36#include <asm/addrspace.h>
37
38#include <asm/mach-au1x00/au1000.h>
39#include <asm/gpio.h>
25 40
26#define gpio1 sys 41#define gpio1 sys
27#if !defined(CONFIG_SOC_AU1000) 42#if !defined(CONFIG_SOC_AU1000)
28static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
29 43
30#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 44static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
45#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
31 46
32int au1xxx_gpio2_read(int signal) 47static int au1xxx_gpio2_read(unsigned gpio)
33{ 48{
34 signal -= 200; 49 gpio -= AU1XXX_GPIO_BASE;
35/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */ 50 return ((gpio2->pinstate >> gpio) & 0x01);
36 return ((gpio2->pinstate >> signal) & 0x01);
37} 51}
38 52
39void au1xxx_gpio2_write(int signal, int value) 53static void au1xxx_gpio2_write(unsigned gpio, int value)
40{ 54{
41 signal -= 200; 55 gpio -= AU1XXX_GPIO_BASE;
42 56
43 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) | 57 gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio);
44 (value << signal);
45} 58}
46 59
47void au1xxx_gpio2_tristate(int signal) 60static int au1xxx_gpio2_direction_input(unsigned gpio)
48{ 61{
49 signal -= 200; 62 gpio -= AU1XXX_GPIO_BASE;
50 gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */ 63 gpio2->dir &= ~(0x01 << gpio);
64 return 0;
51} 65}
52#endif
53 66
54int au1xxx_gpio1_read(int signal) 67static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
68{
69 gpio -= AU1XXX_GPIO_BASE;
70 gpio2->dir = (0x01 << gpio) | (value << gpio);
71 return 0;
72}
73
74#endif /* !defined(CONFIG_SOC_AU1000) */
75
76static int au1xxx_gpio1_read(unsigned gpio)
55{ 77{
56/* gpio1->trioutclr |= (0x01 << signal); */ 78 return ((gpio1->pinstaterd >> gpio) & 0x01);
57 return ((gpio1->pinstaterd >> signal) & 0x01);
58} 79}
59 80
60void au1xxx_gpio1_write(int signal, int value) 81static void au1xxx_gpio1_write(unsigned gpio, int value)
61{ 82{
62 if(value) 83 if (value)
63 gpio1->outputset = (0x01 << signal); 84 gpio1->outputset = (0x01 << gpio);
64 else 85 else
65 gpio1->outputclr = (0x01 << signal); /* Output a Zero */ 86 /* Output a zero */
87 gpio1->outputclr = (0x01 << gpio);
66} 88}
67 89
68void au1xxx_gpio1_tristate(int signal) 90static int au1xxx_gpio1_direction_input(unsigned gpio)
69{ 91{
70 gpio1->trioutclr = (0x01 << signal); /* Tristate signal */ 92 gpio1->pininputen = (0x01 << gpio);
93 return 0;
71} 94}
72 95
96static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
97{
98 gpio1->trioutclr = (0x01 & gpio);
99 return 0;
100}
73 101
74int au1xxx_gpio_read(int signal) 102int au1xxx_gpio_get_value(unsigned gpio)
75{ 103{
76 if(signal >= 200) 104 if (gpio >= AU1XXX_GPIO_BASE)
77#if defined(CONFIG_SOC_AU1000) 105#if defined(CONFIG_SOC_AU1000)
78 return 0; 106 return 0;
79#else 107#else
80 return au1xxx_gpio2_read(signal); 108 return au1xxx_gpio2_read(gpio);
81#endif 109#endif
82 else 110 else
83 return au1xxx_gpio1_read(signal); 111 return au1xxx_gpio1_read(gpio);
84} 112}
85 113
86void au1xxx_gpio_write(int signal, int value) 114EXPORT_SYMBOL(au1xxx_gpio_get_value);
115
116void au1xxx_gpio_set_value(unsigned gpio, int value)
87{ 117{
88 if(signal >= 200) 118 if (gpio >= AU1XXX_GPIO_BASE)
89#if defined(CONFIG_SOC_AU1000) 119#if defined(CONFIG_SOC_AU1000)
90 ; 120 ;
91#else 121#else
92 au1xxx_gpio2_write(signal, value); 122 au1xxx_gpio2_write(gpio, value);
93#endif 123#endif
94 else 124 else
95 au1xxx_gpio1_write(signal, value); 125 au1xxx_gpio1_write(gpio, value);
96} 126}
97 127
98void au1xxx_gpio_tristate(int signal) 128EXPORT_SYMBOL(au1xxx_gpio_set_value);
129
130int au1xxx_gpio_direction_input(unsigned gpio)
99{ 131{
100 if(signal >= 200) 132 if (gpio >= AU1XXX_GPIO_BASE)
101#if defined(CONFIG_SOC_AU1000) 133#if defined(CONFIG_SOC_AU1000)
102 ; 134 ;
103#else 135#else
104 au1xxx_gpio2_tristate(signal); 136 return au1xxx_gpio2_direction_input(gpio);
105#endif 137#endif
106 else 138 else
107 au1xxx_gpio1_tristate(signal); 139 return au1xxx_gpio1_direction_input(gpio);
108} 140}
109 141
110void au1xxx_gpio1_set_inputs(void) 142EXPORT_SYMBOL(au1xxx_gpio_direction_input);
143
144int au1xxx_gpio_direction_output(unsigned gpio, int value)
111{ 145{
112 gpio1->pininputen = 0; 146 if (gpio >= AU1XXX_GPIO_BASE)
147#if defined(CONFIG_SOC_AU1000)
148 ;
149#else
150 return au1xxx_gpio2_direction_output(gpio, value);
151#endif
152 else
153 return au1xxx_gpio1_direction_output(gpio, value);
113} 154}
114 155
115EXPORT_SYMBOL(au1xxx_gpio1_set_inputs); 156EXPORT_SYMBOL(au1xxx_gpio_direction_output);
116EXPORT_SYMBOL(au1xxx_gpio_tristate);
117EXPORT_SYMBOL(au1xxx_gpio_write);
118EXPORT_SYMBOL(au1xxx_gpio_read);