diff options
author | Pete Popov <ppopov@embeddedalley.com> | 2005-03-01 01:33:16 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:30:47 -0400 |
commit | e3ad1c23ba72214669b364c6fa304531dc768c3e (patch) | |
tree | bc1e0004d3df66b4c37a2deb8d89431657039719 /arch/mips/au1000/common/au1xxx_irqmap.c | |
parent | 784f7b9d895893c6aa3ca471c1344a62fc29c285 (diff) |
Base Au1200 2.6 support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000/common/au1xxx_irqmap.c')
-rw-r--r-- | arch/mips/au1000/common/au1xxx_irqmap.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c index 8a0f39f67c59..0b2c03c52319 100644 --- a/arch/mips/au1000/common/au1xxx_irqmap.c +++ b/arch/mips/au1000/common/au1xxx_irqmap.c | |||
@@ -173,14 +173,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { | |||
173 | { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, | 173 | { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, |
174 | { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, | 174 | { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0}, |
175 | { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, | 175 | { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0}, |
176 | { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 176 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
177 | { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 177 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
178 | { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 178 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
179 | { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | 179 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, |
180 | { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | 180 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, |
181 | { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 181 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
182 | { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 182 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
183 | { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | 183 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
184 | { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, | 184 | { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0}, |
185 | { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, | 185 | { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 }, |
186 | { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, | 186 | { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 }, |
@@ -201,14 +201,14 @@ au1xxx_irq_map_t au1xxx_ic0_map[] = { | |||
201 | { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, | 201 | { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0}, |
202 | { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, | 202 | { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0}, |
203 | { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, | 203 | { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0}, |
204 | { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 }, | 204 | { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 }, |
205 | { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 205 | { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
206 | { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 206 | { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
207 | { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, | 207 | { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 }, |
208 | { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 }, | 208 | { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 }, |
209 | { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, | 209 | { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 }, |
210 | { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, | 210 | { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 }, |
211 | { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, | 211 | { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 }, |
212 | { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, | 212 | { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0}, |
213 | { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, | 213 | { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 }, |
214 | { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, | 214 | { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0}, |