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authorGabor Juhos <juhosg@openwrt.org>2013-08-28 04:41:46 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-09-03 17:22:18 -0400
commit6612a6885b47e73a55d159e5aa4654de89fbfc29 (patch)
tree15c13fcecfe573e671e54ea42ff44d15d2cae673 /arch/mips/ath79
parent59a8c10b253358bebb263540e7ad67e986d66277 (diff)
MIPS: ath79: Use local variables for clock rates
Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath79')
-rw-r--r--arch/mips/ath79/clock.c158
1 files changed, 106 insertions, 52 deletions
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index ebd4340cdc8f..375cb77e7639 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -40,25 +40,34 @@ static struct clk ath79_uart_clk;
40 40
41static void __init ar71xx_clocks_init(void) 41static void __init ar71xx_clocks_init(void)
42{ 42{
43 unsigned long ref_rate;
44 unsigned long cpu_rate;
45 unsigned long ddr_rate;
46 unsigned long ahb_rate;
43 u32 pll; 47 u32 pll;
44 u32 freq; 48 u32 freq;
45 u32 div; 49 u32 div;
46 50
47 ath79_ref_clk.rate = AR71XX_BASE_FREQ; 51 ref_rate = AR71XX_BASE_FREQ;
48 52
49 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); 53 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
50 54
51 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; 55 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
52 freq = div * ath79_ref_clk.rate; 56 freq = div * ref_rate;
53 57
54 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 58 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
55 ath79_cpu_clk.rate = freq / div; 59 cpu_rate = freq / div;
56 60
57 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 61 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
58 ath79_ddr_clk.rate = freq / div; 62 ddr_rate = freq / div;
59 63
60 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 64 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
61 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; 65 ahb_rate = cpu_rate / div;
66
67 ath79_ref_clk.rate = ref_rate;
68 ath79_cpu_clk.rate = cpu_rate;
69 ath79_ddr_clk.rate = ddr_rate;
70 ath79_ahb_clk.rate = ahb_rate;
62 71
63 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 72 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
64 ath79_uart_clk.rate = ath79_ahb_clk.rate; 73 ath79_uart_clk.rate = ath79_ahb_clk.rate;
@@ -66,26 +75,35 @@ static void __init ar71xx_clocks_init(void)
66 75
67static void __init ar724x_clocks_init(void) 76static void __init ar724x_clocks_init(void)
68{ 77{
78 unsigned long ref_rate;
79 unsigned long cpu_rate;
80 unsigned long ddr_rate;
81 unsigned long ahb_rate;
69 u32 pll; 82 u32 pll;
70 u32 freq; 83 u32 freq;
71 u32 div; 84 u32 div;
72 85
73 ath79_ref_clk.rate = AR724X_BASE_FREQ; 86 ref_rate = AR724X_BASE_FREQ;
74 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); 87 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
75 88
76 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); 89 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
77 freq = div * ath79_ref_clk.rate; 90 freq = div * ref_rate;
78 91
79 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); 92 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
80 freq *= div; 93 freq *= div;
81 94
82 ath79_cpu_clk.rate = freq; 95 cpu_rate = freq;
83 96
84 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; 97 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
85 ath79_ddr_clk.rate = freq / div; 98 ddr_rate = freq / div;
86 99
87 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; 100 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
88 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; 101 ahb_rate = cpu_rate / div;
102
103 ath79_ref_clk.rate = ref_rate;
104 ath79_cpu_clk.rate = cpu_rate;
105 ath79_ddr_clk.rate = ddr_rate;
106 ath79_ahb_clk.rate = ahb_rate;
89 107
90 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 108 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
91 ath79_uart_clk.rate = ath79_ahb_clk.rate; 109 ath79_uart_clk.rate = ath79_ahb_clk.rate;
@@ -93,23 +111,32 @@ static void __init ar724x_clocks_init(void)
93 111
94static void __init ar913x_clocks_init(void) 112static void __init ar913x_clocks_init(void)
95{ 113{
114 unsigned long ref_rate;
115 unsigned long cpu_rate;
116 unsigned long ddr_rate;
117 unsigned long ahb_rate;
96 u32 pll; 118 u32 pll;
97 u32 freq; 119 u32 freq;
98 u32 div; 120 u32 div;
99 121
100 ath79_ref_clk.rate = AR913X_BASE_FREQ; 122 ref_rate = AR913X_BASE_FREQ;
101 pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); 123 pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
102 124
103 div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); 125 div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
104 freq = div * ath79_ref_clk.rate; 126 freq = div * ref_rate;
105 127
106 ath79_cpu_clk.rate = freq; 128 cpu_rate = freq;
107 129
108 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; 130 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
109 ath79_ddr_clk.rate = freq / div; 131 ddr_rate = freq / div;
110 132
111 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; 133 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
112 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; 134 ahb_rate = cpu_rate / div;
135
136 ath79_ref_clk.rate = ref_rate;
137 ath79_cpu_clk.rate = cpu_rate;
138 ath79_ddr_clk.rate = ddr_rate;
139 ath79_ahb_clk.rate = ahb_rate;
113 140
114 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 141 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
115 ath79_uart_clk.rate = ath79_ahb_clk.rate; 142 ath79_uart_clk.rate = ath79_ahb_clk.rate;
@@ -117,6 +144,10 @@ static void __init ar913x_clocks_init(void)
117 144
118static void __init ar933x_clocks_init(void) 145static void __init ar933x_clocks_init(void)
119{ 146{
147 unsigned long ref_rate;
148 unsigned long cpu_rate;
149 unsigned long ddr_rate;
150 unsigned long ahb_rate;
120 u32 clock_ctrl; 151 u32 clock_ctrl;
121 u32 cpu_config; 152 u32 cpu_config;
122 u32 freq; 153 u32 freq;
@@ -124,21 +155,21 @@ static void __init ar933x_clocks_init(void)
124 155
125 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 156 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
126 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 157 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
127 ath79_ref_clk.rate = (40 * 1000 * 1000); 158 ref_rate = (40 * 1000 * 1000);
128 else 159 else
129 ath79_ref_clk.rate = (25 * 1000 * 1000); 160 ref_rate = (25 * 1000 * 1000);
130 161
131 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); 162 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
132 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { 163 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
133 ath79_cpu_clk.rate = ath79_ref_clk.rate; 164 cpu_rate = ref_rate;
134 ath79_ahb_clk.rate = ath79_ref_clk.rate; 165 ahb_rate = ref_rate;
135 ath79_ddr_clk.rate = ath79_ref_clk.rate; 166 ddr_rate = ref_rate;
136 } else { 167 } else {
137 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); 168 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
138 169
139 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 170 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
140 AR933X_PLL_CPU_CONFIG_REFDIV_MASK; 171 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
141 freq = ath79_ref_clk.rate / t; 172 freq = ref_rate / t;
142 173
143 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & 174 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
144 AR933X_PLL_CPU_CONFIG_NINT_MASK; 175 AR933X_PLL_CPU_CONFIG_NINT_MASK;
@@ -153,17 +184,22 @@ static void __init ar933x_clocks_init(void)
153 184
154 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & 185 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
155 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; 186 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
156 ath79_cpu_clk.rate = freq / t; 187 cpu_rate = freq / t;
157 188
158 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & 189 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
159 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; 190 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
160 ath79_ddr_clk.rate = freq / t; 191 ddr_rate = freq / t;
161 192
162 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & 193 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
163 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; 194 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
164 ath79_ahb_clk.rate = freq / t; 195 ahb_rate = freq / t;
165 } 196 }
166 197
198 ath79_ref_clk.rate = ref_rate;
199 ath79_cpu_clk.rate = cpu_rate;
200 ath79_ddr_clk.rate = ddr_rate;
201 ath79_ahb_clk.rate = ahb_rate;
202
167 ath79_wdt_clk.rate = ath79_ahb_clk.rate; 203 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
168 ath79_uart_clk.rate = ath79_ref_clk.rate; 204 ath79_uart_clk.rate = ath79_ref_clk.rate;
169} 205}
@@ -190,6 +226,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
190 226
191static void __init ar934x_clocks_init(void) 227static void __init ar934x_clocks_init(void)
192{ 228{
229 unsigned long ref_rate;
230 unsigned long cpu_rate;
231 unsigned long ddr_rate;
232 unsigned long ahb_rate;
193 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; 233 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
194 u32 cpu_pll, ddr_pll; 234 u32 cpu_pll, ddr_pll;
195 u32 bootstrap; 235 u32 bootstrap;
@@ -199,9 +239,9 @@ static void __init ar934x_clocks_init(void)
199 239
200 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 240 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
201 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) 241 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
202 ath79_ref_clk.rate = 40 * 1000 * 1000; 242 ref_rate = 40 * 1000 * 1000;
203 else 243 else
204 ath79_ref_clk.rate = 25 * 1000 * 1000; 244 ref_rate = 25 * 1000 * 1000;
205 245
206 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); 246 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
207 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 247 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
@@ -227,7 +267,7 @@ static void __init ar934x_clocks_init(void)
227 frac = 1 << 6; 267 frac = 1 << 6;
228 } 268 }
229 269
230 cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, 270 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
231 nfrac, frac, out_div); 271 nfrac, frac, out_div);
232 272
233 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); 273 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
@@ -254,7 +294,7 @@ static void __init ar934x_clocks_init(void)
254 frac = 1 << 10; 294 frac = 1 << 10;
255 } 295 }
256 296
257 ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, 297 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
258 nfrac, frac, out_div); 298 nfrac, frac, out_div);
259 299
260 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); 300 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
@@ -263,31 +303,36 @@ static void __init ar934x_clocks_init(void)
263 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; 303 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
264 304
265 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) 305 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
266 ath79_cpu_clk.rate = ath79_ref_clk.rate; 306 cpu_rate = ref_rate;
267 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) 307 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
268 ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); 308 cpu_rate = cpu_pll / (postdiv + 1);
269 else 309 else
270 ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); 310 cpu_rate = ddr_pll / (postdiv + 1);
271 311
272 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & 312 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
273 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; 313 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
274 314
275 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) 315 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
276 ath79_ddr_clk.rate = ath79_ref_clk.rate; 316 ddr_rate = ref_rate;
277 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) 317 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
278 ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); 318 ddr_rate = ddr_pll / (postdiv + 1);
279 else 319 else
280 ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); 320 ddr_rate = cpu_pll / (postdiv + 1);
281 321
282 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & 322 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
283 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; 323 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
284 324
285 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) 325 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
286 ath79_ahb_clk.rate = ath79_ref_clk.rate; 326 ahb_rate = ref_rate;
287 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) 327 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
288 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); 328 ahb_rate = ddr_pll / (postdiv + 1);
289 else 329 else
290 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); 330 ahb_rate = cpu_pll / (postdiv + 1);
331
332 ath79_ref_clk.rate = ref_rate;
333 ath79_cpu_clk.rate = cpu_rate;
334 ath79_ddr_clk.rate = ddr_rate;
335 ath79_ahb_clk.rate = ahb_rate;
291 336
292 ath79_wdt_clk.rate = ath79_ref_clk.rate; 337 ath79_wdt_clk.rate = ath79_ref_clk.rate;
293 ath79_uart_clk.rate = ath79_ref_clk.rate; 338 ath79_uart_clk.rate = ath79_ref_clk.rate;
@@ -297,15 +342,19 @@ static void __init ar934x_clocks_init(void)
297 342
298static void __init qca955x_clocks_init(void) 343static void __init qca955x_clocks_init(void)
299{ 344{
345 unsigned long ref_rate;
346 unsigned long cpu_rate;
347 unsigned long ddr_rate;
348 unsigned long ahb_rate;
300 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 349 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
301 u32 cpu_pll, ddr_pll; 350 u32 cpu_pll, ddr_pll;
302 u32 bootstrap; 351 u32 bootstrap;
303 352
304 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); 353 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
305 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) 354 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
306 ath79_ref_clk.rate = 40 * 1000 * 1000; 355 ref_rate = 40 * 1000 * 1000;
307 else 356 else
308 ath79_ref_clk.rate = 25 * 1000 * 1000; 357 ref_rate = 25 * 1000 * 1000;
309 358
310 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); 359 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
311 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 360 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
@@ -317,8 +366,8 @@ static void __init qca955x_clocks_init(void)
317 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 366 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
318 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; 367 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
319 368
320 cpu_pll = nint * ath79_ref_clk.rate / ref_div; 369 cpu_pll = nint * ref_rate / ref_div;
321 cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); 370 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
322 cpu_pll /= (1 << out_div); 371 cpu_pll /= (1 << out_div);
323 372
324 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); 373 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
@@ -331,8 +380,8 @@ static void __init qca955x_clocks_init(void)
331 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 380 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
332 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; 381 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
333 382
334 ddr_pll = nint * ath79_ref_clk.rate / ref_div; 383 ddr_pll = nint * ref_rate / ref_div;
335 ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); 384 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
336 ddr_pll /= (1 << out_div); 385 ddr_pll /= (1 << out_div);
337 386
338 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); 387 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
@@ -341,31 +390,36 @@ static void __init qca955x_clocks_init(void)
341 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; 390 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
342 391
343 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) 392 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
344 ath79_cpu_clk.rate = ath79_ref_clk.rate; 393 cpu_rate = ref_rate;
345 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) 394 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
346 ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); 395 cpu_rate = ddr_pll / (postdiv + 1);
347 else 396 else
348 ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); 397 cpu_rate = cpu_pll / (postdiv + 1);
349 398
350 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & 399 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
351 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; 400 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
352 401
353 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) 402 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
354 ath79_ddr_clk.rate = ath79_ref_clk.rate; 403 ddr_rate = ref_rate;
355 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) 404 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
356 ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); 405 ddr_rate = cpu_pll / (postdiv + 1);
357 else 406 else
358 ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); 407 ddr_rate = ddr_pll / (postdiv + 1);
359 408
360 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & 409 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
361 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; 410 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
362 411
363 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) 412 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
364 ath79_ahb_clk.rate = ath79_ref_clk.rate; 413 ahb_rate = ref_rate;
365 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) 414 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
366 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); 415 ahb_rate = ddr_pll / (postdiv + 1);
367 else 416 else
368 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); 417 ahb_rate = cpu_pll / (postdiv + 1);
418
419 ath79_ref_clk.rate = ref_rate;
420 ath79_cpu_clk.rate = cpu_rate;
421 ath79_ddr_clk.rate = ddr_rate;
422 ath79_ahb_clk.rate = ahb_rate;
369 423
370 ath79_wdt_clk.rate = ath79_ref_clk.rate; 424 ath79_wdt_clk.rate = ath79_ref_clk.rate;
371 ath79_uart_clk.rate = ath79_ref_clk.rate; 425 ath79_uart_clk.rate = ath79_ref_clk.rate;