MIPS: ath79: add PCI controller registration code for the QCA955X SoCs

Add SoC specific PCI IRQ map, and register platform
devices for the two built-in PCIe RCs.

Cc: Rodriguez, Luis <rodrigue@qca.qualcomm.com>
Cc: Giori, Kathy <kgiori@qca.qualcomm.com>
Cc: QCA Linux Team <qca-linux-team@qca.qualcomm.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4951/
Signed-off-by: John Crispin <blogic@openwrt.org>

1 files changed, 36 insertions, 0 deletions

diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c
index 4350c252bce5..730c0b03060d 100644
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
         }
 };
 
+static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
+        {
+                .bus    = 0,
+                .slot   = 0,
+                .pin    = 1,
+                .irq    = ATH79_PCI_IRQ(0),
+        },
+        {
+                .bus    = 1,
+                .slot   = 0,
+                .pin    = 1,
+                .irq    = ATH79_PCI_IRQ(1),
+        },
+};
+
 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 {
         int irq = -1;
@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
                            soc_is_ar9344()) {
                         ath79_pci_irq_map = ar724x_pci_irq_map;
                         ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+                } else if (soc_is_qca955x()) {
+                        ath79_pci_irq_map = qca955x_pci_irq_map;
+                        ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
                 } else {
                         pr_crit("pci %s: invalid irq map\n",
                                 pci_name((struct pci_dev *) dev));
@@ -225,6 +243,24 @@ int __init ath79_register_pci(void)
                                                  AR724X_PCI_MEM_SIZE,
                                                  0,
                                                  ATH79_IP2_IRQ(0));
+        } else if (soc_is_qca9558()) {
+                pdev = ath79_register_pci_ar724x(0,
+                                                 QCA955X_PCI_CFG_BASE0,
+                                                 QCA955X_PCI_CTRL_BASE0,
+                                                 QCA955X_PCI_CRP_BASE0,
+                                                 QCA955X_PCI_MEM_BASE0,
+                                                 QCA955X_PCI_MEM_SIZE,
+                                                 0,
+                                                 ATH79_IP2_IRQ(0));
+
+                pdev = ath79_register_pci_ar724x(1,
+                                                 QCA955X_PCI_CFG_BASE1,
+                                                 QCA955X_PCI_CTRL_BASE1,
+                                                 QCA955X_PCI_CRP_BASE1,
+                                                 QCA955X_PCI_MEM_BASE1,
+                                                 QCA955X_PCI_MEM_SIZE,
+                                                 1,
+                                                 ATH79_IP3_IRQ(2));
         } else {
                 /* No PCI support */
                 return -ENODEV;