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authorFlorian Fainelli <florian@openwrt.org>2010-05-16 09:25:17 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-07-05 12:17:17 -0400
commit154615d554596d96dd2b29bba4116fa21770fdc0 (patch)
treea5b29e482ed7c9f39e75f81435f0d3258a9b35fa /arch/mips/ar7/platform.c
parent984bc9601f64fd341b8573021d7c999f1f1499a9 (diff)
MIPS: AR7: Use correct UART port type
PORT_AR7 has the correct TRIG flag (UART_FCR_R_TRIG_00) as well as UART_CAP_AFE being set. This fixes UART on TNETD7300 revision 0x02, which would otherwise mangle some characters, no side effects on other revisions. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1246/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ar7/platform.c')
-rw-r--r--arch/mips/ar7/platform.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 566f2d7f2ea3..8f31d1d59683 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -542,7 +542,7 @@ static int __init ar7_register_uarts(void)
542 if (IS_ERR(bus_clk)) 542 if (IS_ERR(bus_clk))
543 panic("unable to get bus clk\n"); 543 panic("unable to get bus clk\n");
544 544
545 uart_port.type = PORT_16550A; 545 uart_port.type = PORT_AR7;
546 uart_port.uartclk = clk_get_rate(bus_clk) / 2; 546 uart_port.uartclk = clk_get_rate(bus_clk) / 2;
547 uart_port.iotype = UPIO_MEM32; 547 uart_port.iotype = UPIO_MEM32;
548 uart_port.regshift = 2; 548 uart_port.regshift = 2;