diff options
author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-05-08 04:42:14 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 04:55:45 -0400 |
commit | dca7587185b3a499a09a9e2755316eee31c49c7f (patch) | |
tree | eec8c9040216496d64493719b759176083b5b95d /arch/mips/alchemy | |
parent | c1e58a3129bc327f7e0eb06fd4fe5ebf2af5d8ef (diff) |
MIPS: Alchemy: irq code and constant cleanup
replace au_readl/au_writel with __raw_readl/__raw_writel,
and clean up IC-related stuff from the headers.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Patchwork: https://patchwork.linux-mips.org/patch/2354/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r-- | arch/mips/alchemy/common/irq.c | 250 |
1 files changed, 135 insertions, 115 deletions
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 55dd7c888517..b72e12829480 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c | |||
@@ -39,6 +39,36 @@ | |||
39 | #include <asm/mach-pb1x00/pb1000.h> | 39 | #include <asm/mach-pb1x00/pb1000.h> |
40 | #endif | 40 | #endif |
41 | 41 | ||
42 | /* Interrupt Controller register offsets */ | ||
43 | #define IC_CFG0RD 0x40 | ||
44 | #define IC_CFG0SET 0x40 | ||
45 | #define IC_CFG0CLR 0x44 | ||
46 | #define IC_CFG1RD 0x48 | ||
47 | #define IC_CFG1SET 0x48 | ||
48 | #define IC_CFG1CLR 0x4C | ||
49 | #define IC_CFG2RD 0x50 | ||
50 | #define IC_CFG2SET 0x50 | ||
51 | #define IC_CFG2CLR 0x54 | ||
52 | #define IC_REQ0INT 0x54 | ||
53 | #define IC_SRCRD 0x58 | ||
54 | #define IC_SRCSET 0x58 | ||
55 | #define IC_SRCCLR 0x5C | ||
56 | #define IC_REQ1INT 0x5C | ||
57 | #define IC_ASSIGNRD 0x60 | ||
58 | #define IC_ASSIGNSET 0x60 | ||
59 | #define IC_ASSIGNCLR 0x64 | ||
60 | #define IC_WAKERD 0x68 | ||
61 | #define IC_WAKESET 0x68 | ||
62 | #define IC_WAKECLR 0x6C | ||
63 | #define IC_MASKRD 0x70 | ||
64 | #define IC_MASKSET 0x70 | ||
65 | #define IC_MASKCLR 0x74 | ||
66 | #define IC_RISINGRD 0x78 | ||
67 | #define IC_RISINGCLR 0x78 | ||
68 | #define IC_FALLINGRD 0x7C | ||
69 | #define IC_FALLINGCLR 0x7C | ||
70 | #define IC_TESTBIT 0x80 | ||
71 | |||
42 | static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); | 72 | static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type); |
43 | 73 | ||
44 | /* NOTE on interrupt priorities: The original writers of this code said: | 74 | /* NOTE on interrupt priorities: The original writers of this code said: |
@@ -221,89 +251,101 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { | |||
221 | static void au1x_ic0_unmask(struct irq_data *d) | 251 | static void au1x_ic0_unmask(struct irq_data *d) |
222 | { | 252 | { |
223 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; | 253 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; |
224 | au_writel(1 << bit, IC0_MASKSET); | 254 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); |
225 | au_writel(1 << bit, IC0_WAKESET); | 255 | |
226 | au_sync(); | 256 | __raw_writel(1 << bit, base + IC_MASKSET); |
257 | __raw_writel(1 << bit, base + IC_WAKESET); | ||
258 | wmb(); | ||
227 | } | 259 | } |
228 | 260 | ||
229 | static void au1x_ic1_unmask(struct irq_data *d) | 261 | static void au1x_ic1_unmask(struct irq_data *d) |
230 | { | 262 | { |
231 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; | 263 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; |
232 | au_writel(1 << bit, IC1_MASKSET); | 264 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); |
233 | au_writel(1 << bit, IC1_WAKESET); | 265 | |
266 | __raw_writel(1 << bit, base + IC_MASKSET); | ||
267 | __raw_writel(1 << bit, base + IC_WAKESET); | ||
234 | 268 | ||
235 | /* very hacky. does the pb1000 cpld auto-disable this int? | 269 | /* very hacky. does the pb1000 cpld auto-disable this int? |
236 | * nowhere in the current kernel sources is it disabled. --mlau | 270 | * nowhere in the current kernel sources is it disabled. --mlau |
237 | */ | 271 | */ |
238 | #if defined(CONFIG_MIPS_PB1000) | 272 | #if defined(CONFIG_MIPS_PB1000) |
239 | if (d->irq == AU1000_GPIO15_INT) | 273 | if (d->irq == AU1000_GPIO15_INT) |
240 | au_writel(0x4000, PB1000_MDR); /* enable int */ | 274 | __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */ |
241 | #endif | 275 | #endif |
242 | au_sync(); | 276 | wmb(); |
243 | } | 277 | } |
244 | 278 | ||
245 | static void au1x_ic0_mask(struct irq_data *d) | 279 | static void au1x_ic0_mask(struct irq_data *d) |
246 | { | 280 | { |
247 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; | 281 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; |
248 | au_writel(1 << bit, IC0_MASKCLR); | 282 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); |
249 | au_writel(1 << bit, IC0_WAKECLR); | 283 | |
250 | au_sync(); | 284 | __raw_writel(1 << bit, base + IC_MASKCLR); |
285 | __raw_writel(1 << bit, base + IC_WAKECLR); | ||
286 | wmb(); | ||
251 | } | 287 | } |
252 | 288 | ||
253 | static void au1x_ic1_mask(struct irq_data *d) | 289 | static void au1x_ic1_mask(struct irq_data *d) |
254 | { | 290 | { |
255 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; | 291 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; |
256 | au_writel(1 << bit, IC1_MASKCLR); | 292 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); |
257 | au_writel(1 << bit, IC1_WAKECLR); | 293 | |
258 | au_sync(); | 294 | __raw_writel(1 << bit, base + IC_MASKCLR); |
295 | __raw_writel(1 << bit, base + IC_WAKECLR); | ||
296 | wmb(); | ||
259 | } | 297 | } |
260 | 298 | ||
261 | static void au1x_ic0_ack(struct irq_data *d) | 299 | static void au1x_ic0_ack(struct irq_data *d) |
262 | { | 300 | { |
263 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; | 301 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; |
302 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); | ||
264 | 303 | ||
265 | /* | 304 | /* |
266 | * This may assume that we don't get interrupts from | 305 | * This may assume that we don't get interrupts from |
267 | * both edges at once, or if we do, that we don't care. | 306 | * both edges at once, or if we do, that we don't care. |
268 | */ | 307 | */ |
269 | au_writel(1 << bit, IC0_FALLINGCLR); | 308 | __raw_writel(1 << bit, base + IC_FALLINGCLR); |
270 | au_writel(1 << bit, IC0_RISINGCLR); | 309 | __raw_writel(1 << bit, base + IC_RISINGCLR); |
271 | au_sync(); | 310 | wmb(); |
272 | } | 311 | } |
273 | 312 | ||
274 | static void au1x_ic1_ack(struct irq_data *d) | 313 | static void au1x_ic1_ack(struct irq_data *d) |
275 | { | 314 | { |
276 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; | 315 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; |
316 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); | ||
277 | 317 | ||
278 | /* | 318 | /* |
279 | * This may assume that we don't get interrupts from | 319 | * This may assume that we don't get interrupts from |
280 | * both edges at once, or if we do, that we don't care. | 320 | * both edges at once, or if we do, that we don't care. |
281 | */ | 321 | */ |
282 | au_writel(1 << bit, IC1_FALLINGCLR); | 322 | __raw_writel(1 << bit, base + IC_FALLINGCLR); |
283 | au_writel(1 << bit, IC1_RISINGCLR); | 323 | __raw_writel(1 << bit, base + IC_RISINGCLR); |
284 | au_sync(); | 324 | wmb(); |
285 | } | 325 | } |
286 | 326 | ||
287 | static void au1x_ic0_maskack(struct irq_data *d) | 327 | static void au1x_ic0_maskack(struct irq_data *d) |
288 | { | 328 | { |
289 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; | 329 | unsigned int bit = d->irq - AU1000_INTC0_INT_BASE; |
330 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); | ||
290 | 331 | ||
291 | au_writel(1 << bit, IC0_WAKECLR); | 332 | __raw_writel(1 << bit, base + IC_WAKECLR); |
292 | au_writel(1 << bit, IC0_MASKCLR); | 333 | __raw_writel(1 << bit, base + IC_MASKCLR); |
293 | au_writel(1 << bit, IC0_RISINGCLR); | 334 | __raw_writel(1 << bit, base + IC_RISINGCLR); |
294 | au_writel(1 << bit, IC0_FALLINGCLR); | 335 | __raw_writel(1 << bit, base + IC_FALLINGCLR); |
295 | au_sync(); | 336 | wmb(); |
296 | } | 337 | } |
297 | 338 | ||
298 | static void au1x_ic1_maskack(struct irq_data *d) | 339 | static void au1x_ic1_maskack(struct irq_data *d) |
299 | { | 340 | { |
300 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; | 341 | unsigned int bit = d->irq - AU1000_INTC1_INT_BASE; |
342 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); | ||
301 | 343 | ||
302 | au_writel(1 << bit, IC1_WAKECLR); | 344 | __raw_writel(1 << bit, base + IC_WAKECLR); |
303 | au_writel(1 << bit, IC1_MASKCLR); | 345 | __raw_writel(1 << bit, base + IC_MASKCLR); |
304 | au_writel(1 << bit, IC1_RISINGCLR); | 346 | __raw_writel(1 << bit, base + IC_RISINGCLR); |
305 | au_writel(1 << bit, IC1_FALLINGCLR); | 347 | __raw_writel(1 << bit, base + IC_FALLINGCLR); |
306 | au_sync(); | 348 | wmb(); |
307 | } | 349 | } |
308 | 350 | ||
309 | static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) | 351 | static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) |
@@ -318,13 +360,13 @@ static int au1x_ic1_setwake(struct irq_data *d, unsigned int on) | |||
318 | return -EINVAL; | 360 | return -EINVAL; |
319 | 361 | ||
320 | local_irq_save(flags); | 362 | local_irq_save(flags); |
321 | wakemsk = au_readl(SYS_WAKEMSK); | 363 | wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK); |
322 | if (on) | 364 | if (on) |
323 | wakemsk |= 1 << bit; | 365 | wakemsk |= 1 << bit; |
324 | else | 366 | else |
325 | wakemsk &= ~(1 << bit); | 367 | wakemsk &= ~(1 << bit); |
326 | au_writel(wakemsk, SYS_WAKEMSK); | 368 | __raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK); |
327 | au_sync(); | 369 | wmb(); |
328 | local_irq_restore(flags); | 370 | local_irq_restore(flags); |
329 | 371 | ||
330 | return 0; | 372 | return 0; |
@@ -356,81 +398,74 @@ static struct irq_chip au1x_ic1_chip = { | |||
356 | static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type) | 398 | static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type) |
357 | { | 399 | { |
358 | struct irq_chip *chip; | 400 | struct irq_chip *chip; |
359 | unsigned long icr[6]; | 401 | unsigned int bit, irq = d->irq; |
360 | unsigned int bit, ic, irq = d->irq; | ||
361 | irq_flow_handler_t handler = NULL; | 402 | irq_flow_handler_t handler = NULL; |
362 | unsigned char *name = NULL; | 403 | unsigned char *name = NULL; |
404 | void __iomem *base; | ||
363 | int ret; | 405 | int ret; |
364 | 406 | ||
365 | if (irq >= AU1000_INTC1_INT_BASE) { | 407 | if (irq >= AU1000_INTC1_INT_BASE) { |
366 | bit = irq - AU1000_INTC1_INT_BASE; | 408 | bit = irq - AU1000_INTC1_INT_BASE; |
367 | chip = &au1x_ic1_chip; | 409 | chip = &au1x_ic1_chip; |
368 | ic = 1; | 410 | base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); |
369 | } else { | 411 | } else { |
370 | bit = irq - AU1000_INTC0_INT_BASE; | 412 | bit = irq - AU1000_INTC0_INT_BASE; |
371 | chip = &au1x_ic0_chip; | 413 | chip = &au1x_ic0_chip; |
372 | ic = 0; | 414 | base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); |
373 | } | 415 | } |
374 | 416 | ||
375 | if (bit > 31) | 417 | if (bit > 31) |
376 | return -EINVAL; | 418 | return -EINVAL; |
377 | 419 | ||
378 | icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET; | ||
379 | icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET; | ||
380 | icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET; | ||
381 | icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR; | ||
382 | icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR; | ||
383 | icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR; | ||
384 | |||
385 | ret = 0; | 420 | ret = 0; |
386 | 421 | ||
387 | switch (flow_type) { /* cfgregs 2:1:0 */ | 422 | switch (flow_type) { /* cfgregs 2:1:0 */ |
388 | case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ | 423 | case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */ |
389 | au_writel(1 << bit, icr[5]); | 424 | __raw_writel(1 << bit, base + IC_CFG2CLR); |
390 | au_writel(1 << bit, icr[4]); | 425 | __raw_writel(1 << bit, base + IC_CFG1CLR); |
391 | au_writel(1 << bit, icr[0]); | 426 | __raw_writel(1 << bit, base + IC_CFG0SET); |
392 | handler = handle_edge_irq; | 427 | handler = handle_edge_irq; |
393 | name = "riseedge"; | 428 | name = "riseedge"; |
394 | break; | 429 | break; |
395 | case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ | 430 | case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ |
396 | au_writel(1 << bit, icr[5]); | 431 | __raw_writel(1 << bit, base + IC_CFG2CLR); |
397 | au_writel(1 << bit, icr[1]); | 432 | __raw_writel(1 << bit, base + IC_CFG1SET); |
398 | au_writel(1 << bit, icr[3]); | 433 | __raw_writel(1 << bit, base + IC_CFG0CLR); |
399 | handler = handle_edge_irq; | 434 | handler = handle_edge_irq; |
400 | name = "falledge"; | 435 | name = "falledge"; |
401 | break; | 436 | break; |
402 | case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ | 437 | case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ |
403 | au_writel(1 << bit, icr[5]); | 438 | __raw_writel(1 << bit, base + IC_CFG2CLR); |
404 | au_writel(1 << bit, icr[1]); | 439 | __raw_writel(1 << bit, base + IC_CFG1SET); |
405 | au_writel(1 << bit, icr[0]); | 440 | __raw_writel(1 << bit, base + IC_CFG0SET); |
406 | handler = handle_edge_irq; | 441 | handler = handle_edge_irq; |
407 | name = "bothedge"; | 442 | name = "bothedge"; |
408 | break; | 443 | break; |
409 | case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ | 444 | case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ |
410 | au_writel(1 << bit, icr[2]); | 445 | __raw_writel(1 << bit, base + IC_CFG2SET); |
411 | au_writel(1 << bit, icr[4]); | 446 | __raw_writel(1 << bit, base + IC_CFG1CLR); |
412 | au_writel(1 << bit, icr[0]); | 447 | __raw_writel(1 << bit, base + IC_CFG0SET); |
413 | handler = handle_level_irq; | 448 | handler = handle_level_irq; |
414 | name = "hilevel"; | 449 | name = "hilevel"; |
415 | break; | 450 | break; |
416 | case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ | 451 | case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ |
417 | au_writel(1 << bit, icr[2]); | 452 | __raw_writel(1 << bit, base + IC_CFG2SET); |
418 | au_writel(1 << bit, icr[1]); | 453 | __raw_writel(1 << bit, base + IC_CFG1SET); |
419 | au_writel(1 << bit, icr[3]); | 454 | __raw_writel(1 << bit, base + IC_CFG0CLR); |
420 | handler = handle_level_irq; | 455 | handler = handle_level_irq; |
421 | name = "lowlevel"; | 456 | name = "lowlevel"; |
422 | break; | 457 | break; |
423 | case IRQ_TYPE_NONE: /* 0:0:0 */ | 458 | case IRQ_TYPE_NONE: /* 0:0:0 */ |
424 | au_writel(1 << bit, icr[5]); | 459 | __raw_writel(1 << bit, base + IC_CFG2CLR); |
425 | au_writel(1 << bit, icr[4]); | 460 | __raw_writel(1 << bit, base + IC_CFG1CLR); |
426 | au_writel(1 << bit, icr[3]); | 461 | __raw_writel(1 << bit, base + IC_CFG0CLR); |
427 | break; | 462 | break; |
428 | default: | 463 | default: |
429 | ret = -EINVAL; | 464 | ret = -EINVAL; |
430 | } | 465 | } |
431 | __irq_set_chip_handler_name_locked(d->irq, chip, handler, name); | 466 | __irq_set_chip_handler_name_locked(d->irq, chip, handler, name); |
432 | 467 | ||
433 | au_sync(); | 468 | wmb(); |
434 | 469 | ||
435 | return ret; | 470 | return ret; |
436 | } | 471 | } |
@@ -444,21 +479,21 @@ asmlinkage void plat_irq_dispatch(void) | |||
444 | off = MIPS_CPU_IRQ_BASE + 7; | 479 | off = MIPS_CPU_IRQ_BASE + 7; |
445 | goto handle; | 480 | goto handle; |
446 | } else if (pending & CAUSEF_IP2) { | 481 | } else if (pending & CAUSEF_IP2) { |
447 | s = IC0_REQ0INT; | 482 | s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT; |
448 | off = AU1000_INTC0_INT_BASE; | 483 | off = AU1000_INTC0_INT_BASE; |
449 | } else if (pending & CAUSEF_IP3) { | 484 | } else if (pending & CAUSEF_IP3) { |
450 | s = IC0_REQ1INT; | 485 | s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT; |
451 | off = AU1000_INTC0_INT_BASE; | 486 | off = AU1000_INTC0_INT_BASE; |
452 | } else if (pending & CAUSEF_IP4) { | 487 | } else if (pending & CAUSEF_IP4) { |
453 | s = IC1_REQ0INT; | 488 | s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT; |
454 | off = AU1000_INTC1_INT_BASE; | 489 | off = AU1000_INTC1_INT_BASE; |
455 | } else if (pending & CAUSEF_IP5) { | 490 | } else if (pending & CAUSEF_IP5) { |
456 | s = IC1_REQ1INT; | 491 | s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT; |
457 | off = AU1000_INTC1_INT_BASE; | 492 | off = AU1000_INTC1_INT_BASE; |
458 | } else | 493 | } else |
459 | goto spurious; | 494 | goto spurious; |
460 | 495 | ||
461 | s = au_readl(s); | 496 | s = __raw_readl((void __iomem *)s); |
462 | if (unlikely(!s)) { | 497 | if (unlikely(!s)) { |
463 | spurious: | 498 | spurious: |
464 | spurious_interrupt(); | 499 | spurious_interrupt(); |
@@ -469,48 +504,42 @@ handle: | |||
469 | do_IRQ(off); | 504 | do_IRQ(off); |
470 | } | 505 | } |
471 | 506 | ||
507 | |||
508 | static inline void ic_init(void __iomem *base) | ||
509 | { | ||
510 | /* initialize interrupt controller to a safe state */ | ||
511 | __raw_writel(0xffffffff, base + IC_CFG0CLR); | ||
512 | __raw_writel(0xffffffff, base + IC_CFG1CLR); | ||
513 | __raw_writel(0xffffffff, base + IC_CFG2CLR); | ||
514 | __raw_writel(0xffffffff, base + IC_MASKCLR); | ||
515 | __raw_writel(0xffffffff, base + IC_ASSIGNCLR); | ||
516 | __raw_writel(0xffffffff, base + IC_WAKECLR); | ||
517 | __raw_writel(0xffffffff, base + IC_SRCSET); | ||
518 | __raw_writel(0xffffffff, base + IC_FALLINGCLR); | ||
519 | __raw_writel(0xffffffff, base + IC_RISINGCLR); | ||
520 | __raw_writel(0x00000000, base + IC_TESTBIT); | ||
521 | wmb(); | ||
522 | } | ||
523 | |||
472 | static void __init au1000_init_irq(struct au1xxx_irqmap *map) | 524 | static void __init au1000_init_irq(struct au1xxx_irqmap *map) |
473 | { | 525 | { |
474 | unsigned int bit, irq_nr; | 526 | unsigned int bit, irq_nr; |
475 | int i; | 527 | void __iomem *base; |
476 | |||
477 | /* | ||
478 | * Initialize interrupt controllers to a safe state. | ||
479 | */ | ||
480 | au_writel(0xffffffff, IC0_CFG0CLR); | ||
481 | au_writel(0xffffffff, IC0_CFG1CLR); | ||
482 | au_writel(0xffffffff, IC0_CFG2CLR); | ||
483 | au_writel(0xffffffff, IC0_MASKCLR); | ||
484 | au_writel(0xffffffff, IC0_ASSIGNCLR); | ||
485 | au_writel(0xffffffff, IC0_WAKECLR); | ||
486 | au_writel(0xffffffff, IC0_SRCSET); | ||
487 | au_writel(0xffffffff, IC0_FALLINGCLR); | ||
488 | au_writel(0xffffffff, IC0_RISINGCLR); | ||
489 | au_writel(0x00000000, IC0_TESTBIT); | ||
490 | |||
491 | au_writel(0xffffffff, IC1_CFG0CLR); | ||
492 | au_writel(0xffffffff, IC1_CFG1CLR); | ||
493 | au_writel(0xffffffff, IC1_CFG2CLR); | ||
494 | au_writel(0xffffffff, IC1_MASKCLR); | ||
495 | au_writel(0xffffffff, IC1_ASSIGNCLR); | ||
496 | au_writel(0xffffffff, IC1_WAKECLR); | ||
497 | au_writel(0xffffffff, IC1_SRCSET); | ||
498 | au_writel(0xffffffff, IC1_FALLINGCLR); | ||
499 | au_writel(0xffffffff, IC1_RISINGCLR); | ||
500 | au_writel(0x00000000, IC1_TESTBIT); | ||
501 | 528 | ||
529 | ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); | ||
530 | ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); | ||
502 | mips_cpu_irq_init(); | 531 | mips_cpu_irq_init(); |
503 | 532 | ||
504 | /* register all 64 possible IC0+IC1 irq sources as type "none". | 533 | /* register all 64 possible IC0+IC1 irq sources as type "none". |
505 | * Use set_irq_type() to set edge/level behaviour at runtime. | 534 | * Use set_irq_type() to set edge/level behaviour at runtime. |
506 | */ | 535 | */ |
507 | for (i = AU1000_INTC0_INT_BASE; | 536 | for (irq_nr = AU1000_INTC0_INT_BASE; |
508 | (i < AU1000_INTC0_INT_BASE + 32); i++) | 537 | (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++) |
509 | au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); | 538 | au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE); |
510 | 539 | ||
511 | for (i = AU1000_INTC1_INT_BASE; | 540 | for (irq_nr = AU1000_INTC1_INT_BASE; |
512 | (i < AU1000_INTC1_INT_BASE + 32); i++) | 541 | (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++) |
513 | au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); | 542 | au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE); |
514 | 543 | ||
515 | /* | 544 | /* |
516 | * Initialize IC0, which is fixed per processor. | 545 | * Initialize IC0, which is fixed per processor. |
@@ -520,13 +549,13 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) | |||
520 | 549 | ||
521 | if (irq_nr >= AU1000_INTC1_INT_BASE) { | 550 | if (irq_nr >= AU1000_INTC1_INT_BASE) { |
522 | bit = irq_nr - AU1000_INTC1_INT_BASE; | 551 | bit = irq_nr - AU1000_INTC1_INT_BASE; |
523 | if (map->im_request) | 552 | base = (void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR); |
524 | au_writel(1 << bit, IC1_ASSIGNSET); | ||
525 | } else { | 553 | } else { |
526 | bit = irq_nr - AU1000_INTC0_INT_BASE; | 554 | bit = irq_nr - AU1000_INTC0_INT_BASE; |
527 | if (map->im_request) | 555 | base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR); |
528 | au_writel(1 << bit, IC0_ASSIGNSET); | ||
529 | } | 556 | } |
557 | if (map->im_request) | ||
558 | __raw_writel(1 << bit, base + IC_ASSIGNSET); | ||
530 | 559 | ||
531 | au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); | 560 | au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type); |
532 | ++map; | 561 | ++map; |
@@ -583,17 +612,8 @@ static int alchemy_ic_resume(struct sys_device *dev) | |||
583 | struct alchemy_ic_sysdev *icdev = | 612 | struct alchemy_ic_sysdev *icdev = |
584 | container_of(dev, struct alchemy_ic_sysdev, sysdev); | 613 | container_of(dev, struct alchemy_ic_sysdev, sysdev); |
585 | 614 | ||
586 | __raw_writel(0xffffffff, icdev->base + IC_MASKCLR); | 615 | ic_init(icdev->base); |
587 | __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR); | 616 | |
588 | __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR); | ||
589 | __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR); | ||
590 | __raw_writel(0xffffffff, icdev->base + IC_SRCCLR); | ||
591 | __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR); | ||
592 | __raw_writel(0xffffffff, icdev->base + IC_WAKECLR); | ||
593 | __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR); | ||
594 | __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR); | ||
595 | __raw_writel(0x00000000, icdev->base + IC_TESTBIT); | ||
596 | wmb(); | ||
597 | __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); | 617 | __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET); |
598 | __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); | 618 | __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET); |
599 | __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); | 619 | __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET); |
@@ -617,7 +637,7 @@ static struct sysdev_class alchemy_ic_sysdev_class = { | |||
617 | static int __init alchemy_ic_sysdev_init(void) | 637 | static int __init alchemy_ic_sysdev_init(void) |
618 | { | 638 | { |
619 | struct alchemy_ic_sysdev *icdev; | 639 | struct alchemy_ic_sysdev *icdev; |
620 | unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR }; | 640 | unsigned long icbase[2] = { AU1000_IC0_PHYS_ADDR, AU1000_IC1_PHYS_ADDR }; |
621 | int err, i; | 641 | int err, i; |
622 | 642 | ||
623 | err = sysdev_class_register(&alchemy_ic_sysdev_class); | 643 | err = sysdev_class_register(&alchemy_ic_sysdev_class); |