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authorManuel Lauss <manuel.lauss@gmail.com>2014-03-26 05:41:48 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-03-26 18:09:21 -0400
commita16afa53277a961799130ab9189c84adc2d0467e (patch)
treeb509ed78ec8d77ac4930c14dc5a161c001729974 /arch/mips/alchemy
parent970e268d6ed1f1799829cc0c87ea271a9e127e79 (diff)
MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board code
Merge the db1200.h and db1300.h headers into their only users. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/devboards/db1200.c48
-rw-r--r--arch/mips/alchemy/devboards/db1300.c34
2 files changed, 80 insertions, 2 deletions
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index a60d0a3410ea..4bcf2f4e4f93 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -38,13 +38,59 @@
38#include <asm/mach-au1x00/au1000.h> 38#include <asm/mach-au1x00/au1000.h>
39#include <asm/mach-au1x00/au1100_mmc.h> 39#include <asm/mach-au1x00/au1100_mmc.h>
40#include <asm/mach-au1x00/au1xxx_dbdma.h> 40#include <asm/mach-au1x00/au1xxx_dbdma.h>
41#include <asm/mach-au1x00/au1xxx_psc.h>
41#include <asm/mach-au1x00/au1200fb.h> 42#include <asm/mach-au1x00/au1200fb.h>
42#include <asm/mach-au1x00/au1550_spi.h> 43#include <asm/mach-au1x00/au1550_spi.h>
43#include <asm/mach-db1x00/bcsr.h> 44#include <asm/mach-db1x00/bcsr.h>
44#include <asm/mach-db1x00/db1200.h>
45 45
46#include "platform.h" 46#include "platform.h"
47 47
48#define BCSR_INT_IDE 0x0001
49#define BCSR_INT_ETH 0x0002
50#define BCSR_INT_PC0 0x0004
51#define BCSR_INT_PC0STSCHG 0x0008
52#define BCSR_INT_PC1 0x0010
53#define BCSR_INT_PC1STSCHG 0x0020
54#define BCSR_INT_DC 0x0040
55#define BCSR_INT_FLASHBUSY 0x0080
56#define BCSR_INT_PC0INSERT 0x0100
57#define BCSR_INT_PC0EJECT 0x0200
58#define BCSR_INT_PC1INSERT 0x0400
59#define BCSR_INT_PC1EJECT 0x0800
60#define BCSR_INT_SD0INSERT 0x1000
61#define BCSR_INT_SD0EJECT 0x2000
62#define BCSR_INT_SD1INSERT 0x4000
63#define BCSR_INT_SD1EJECT 0x8000
64
65#define DB1200_IDE_PHYS_ADDR 0x18800000
66#define DB1200_IDE_REG_SHIFT 5
67#define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
68#define DB1200_ETH_PHYS_ADDR 0x19000300
69#define DB1200_NAND_PHYS_ADDR 0x20000000
70
71#define PB1200_IDE_PHYS_ADDR 0x0C800000
72#define PB1200_ETH_PHYS_ADDR 0x0D000300
73#define PB1200_NAND_PHYS_ADDR 0x1C000000
74
75#define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
76#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
77#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
78#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
79#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
80#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
81#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
82#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
83#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
84#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
85#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
86#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
87#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
88#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
89#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
90#define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
91#define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
92#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
93
48const char *get_system_type(void); 94const char *get_system_type(void);
49 95
50static int __init db1200_detect_board(void) 96static int __init db1200_detect_board(void)
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index 509602cb463a..1aed6be4de10 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -26,12 +26,44 @@
26#include <asm/mach-au1x00/au1200fb.h> 26#include <asm/mach-au1x00/au1200fb.h>
27#include <asm/mach-au1x00/au1xxx_dbdma.h> 27#include <asm/mach-au1x00/au1xxx_dbdma.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29#include <asm/mach-db1x00/db1300.h>
30#include <asm/mach-db1x00/bcsr.h> 29#include <asm/mach-db1x00/bcsr.h>
31#include <asm/mach-au1x00/prom.h> 30#include <asm/mach-au1x00/prom.h>
32 31
33#include "platform.h" 32#include "platform.h"
34 33
34/* FPGA (external mux) interrupt sources */
35#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
36#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
37#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
38#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
39#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
40#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
41#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
42#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
43#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
44#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
45#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
46#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
47#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
48#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
49#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
50#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
51#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
52
53/* SMSC9210 CS */
54#define DB1300_ETH_PHYS_ADDR 0x19000000
55#define DB1300_ETH_PHYS_END 0x197fffff
56
57/* ATA CS */
58#define DB1300_IDE_PHYS_ADDR 0x18800000
59#define DB1300_IDE_REG_SHIFT 5
60#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
61
62/* NAND CS */
63#define DB1300_NAND_PHYS_ADDR 0x20000000
64#define DB1300_NAND_PHYS_END 0x20000fff
65
66
35static struct i2c_board_info db1300_i2c_devs[] __initdata = { 67static struct i2c_board_info db1300_i2c_devs[] __initdata = {
36 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ 68 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
37 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 69 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */