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authorManuel Lauss <manuel.lauss@googlemail.com>2011-08-12 05:39:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-10-24 18:34:24 -0400
commit7517de348663b08a808aff44b5300e817157a568 (patch)
treeb70b0bdbb30f2ef796c4ca319ad922e7686ca51c /arch/mips/alchemy
parent7cc2e272da3d88c0de9e05b32729402785bd9206 (diff)
MIPS: Alchemy: Redo PCI as platform driver
- Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/Makefile2
-rw-r--r--arch/mips/alchemy/common/pci.c104
-rw-r--r--arch/mips/alchemy/common/setup.c6
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c24
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c123
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c33
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c48
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c6
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c48
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c12
-rw-r--r--arch/mips/alchemy/gpr/platform.c47
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c40
-rw-r--r--arch/mips/alchemy/mtx-1/platform.c62
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c8
14 files changed, 340 insertions, 223 deletions
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 62f0d39e93cd..811ece7b22e3 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -14,5 +14,3 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 14ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
15 obj-$(CONFIG_GPIOLIB) += gpiolib.o 15 obj-$(CONFIG_GPIOLIB) += gpiolib.o
16endif 16endif
17
18obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
deleted file mode 100644
index 7866cf50cf99..000000000000
--- a/arch/mips/alchemy/common/pci.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Alchemy/AMD Au1x00 PCI support.
4 *
5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 *
10 * Support for all devices (greater than 16) added by David Gathright.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#include <linux/pci.h>
34#include <linux/kernel.h>
35#include <linux/init.h>
36
37#include <asm/mach-au1x00/au1000.h>
38
39/* TBD */
40static struct resource pci_io_resource = {
41 .start = PCI_IO_START,
42 .end = PCI_IO_END,
43 .name = "PCI IO space",
44 .flags = IORESOURCE_IO
45};
46
47static struct resource pci_mem_resource = {
48 .start = PCI_MEM_START,
49 .end = PCI_MEM_END,
50 .name = "PCI memory space",
51 .flags = IORESOURCE_MEM
52};
53
54extern struct pci_ops au1x_pci_ops;
55
56static struct pci_controller au1x_controller = {
57 .pci_ops = &au1x_pci_ops,
58 .io_resource = &pci_io_resource,
59 .mem_resource = &pci_mem_resource,
60};
61
62#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
63static unsigned long virt_io_addr;
64#endif
65
66static int __init au1x_pci_setup(void)
67{
68 extern void au1x_pci_cfg_init(void);
69
70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
73
74 if (!virt_io_addr) {
75 printk(KERN_ERR "Unable to ioremap pci space\n");
76 return 1;
77 }
78 au1x_controller.io_map_base = virt_io_addr;
79
80#ifdef CONFIG_DMA_NONCOHERENT
81 {
82 /*
83 * Set the NC bit in controller for Au1500 pre-AC silicon
84 */
85 u32 prid = read_c0_prid();
86
87 if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
88 au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
89 Au1500_PCI_CFG);
90 printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
91 }
92 }
93#endif
94
95 set_io_port_base(virt_io_addr);
96#endif
97
98 au1x_pci_cfg_init();
99
100 register_pci_controller(&au1x_controller);
101 return 0;
102}
103
104arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1b887c868417..37ffd997c616 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -73,8 +73,8 @@ void __init plat_mem_setup(void)
73/* This routine should be valid for all Au1x based boards */ 73/* This routine should be valid for all Au1x based boards */
74phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 74phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
75{ 75{
76 u32 start = (u32)Au1500_PCI_MEM_START; 76 unsigned long start = ALCHEMY_PCI_MEMWIN_START;
77 u32 end = (u32)Au1500_PCI_MEM_END; 77 unsigned long end = ALCHEMY_PCI_MEMWIN_END;
78 78
79 /* Don't fixup 36-bit addresses */ 79 /* Don't fixup 36-bit addresses */
80 if ((phys_addr >> 32) != 0) 80 if ((phys_addr >> 32) != 0)
@@ -82,7 +82,7 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
82 82
83 /* Check for PCI memory window */ 83 /* Check for PCI memory window */
84 if (phys_addr >= start && (phys_addr + size - 1) <= end) 84 if (phys_addr >= start && (phys_addr + size - 1) <= end)
85 return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START); 85 return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
86 86
87 /* default nop */ 87 /* default nop */
88 return phys_addr; 88 return phys_addr;
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 5c956fe8760f..2b2178f3f30b 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -40,24 +40,6 @@
40 40
41#include <prom.h> 41#include <prom.h>
42 42
43#ifdef CONFIG_MIPS_DB1500
44char irq_tab_alchemy[][5] __initdata = {
45 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
46 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
47};
48
49#endif
50
51
52#ifdef CONFIG_MIPS_DB1550
53char irq_tab_alchemy[][5] __initdata = {
54 [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
55 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
56 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
57};
58#endif
59
60
61#ifdef CONFIG_MIPS_BOSPORUS 43#ifdef CONFIG_MIPS_BOSPORUS
62char irq_tab_alchemy[][5] __initdata = { 44char irq_tab_alchemy[][5] __initdata = {
63 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */ 45 [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
@@ -91,12 +73,6 @@ const char *get_system_type(void)
91 73
92 74
93#ifdef CONFIG_MIPS_MIRAGE 75#ifdef CONFIG_MIPS_MIRAGE
94char irq_tab_alchemy[][5] __initdata = {
95 [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
96 [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
97 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
98};
99
100static void mirage_power_off(void) 76static void mirage_power_off(void)
101{ 77{
102 alchemy_gpio_direction_output(210, 1); 78 alchemy_gpio_direction_output(210, 1);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index ef8017f23cdc..9030108928a4 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -25,6 +25,8 @@
25#include <asm/mach-db1x00/bcsr.h> 25#include <asm/mach-db1x00/bcsr.h>
26#include "../platform.h" 26#include "../platform.h"
27 27
28struct pci_dev;
29
28/* DB1xxx PCMCIA interrupt sources: 30/* DB1xxx PCMCIA interrupt sources:
29 * CD0/1 GPIO0/3 31 * CD0/1 GPIO0/3
30 * STSCHG0/1 GPIO1/4 32 * STSCHG0/1 GPIO1/4
@@ -85,6 +87,127 @@
85#endif 87#endif
86#endif 88#endif
87 89
90#ifdef CONFIG_PCI
91#ifdef CONFIG_MIPS_DB1500
92static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
93{
94 if ((slot < 12) || (slot > 13) || pin == 0)
95 return -1;
96 if (slot == 12)
97 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
98 if (slot == 13) {
99 switch (pin) {
100 case 1: return AU1500_PCI_INTA;
101 case 2: return AU1500_PCI_INTB;
102 case 3: return AU1500_PCI_INTC;
103 case 4: return AU1500_PCI_INTD;
104 }
105 }
106 return -1;
107}
108#endif
109
110#ifdef CONFIG_MIPS_DB1550
111static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
112{
113 if ((slot < 11) || (slot > 13) || pin == 0)
114 return -1;
115 if (slot == 11)
116 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
117 if (slot == 12) {
118 switch (pin) {
119 case 1: return AU1550_PCI_INTB;
120 case 2: return AU1550_PCI_INTC;
121 case 3: return AU1550_PCI_INTD;
122 case 4: return AU1550_PCI_INTA;
123 }
124 }
125 if (slot == 13) {
126 switch (pin) {
127 case 1: return AU1550_PCI_INTA;
128 case 2: return AU1550_PCI_INTB;
129 case 3: return AU1550_PCI_INTC;
130 case 4: return AU1550_PCI_INTD;
131 }
132 }
133 return -1;
134}
135#endif
136
137#ifdef CONFIG_MIPS_BOSPORUS
138static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
139{
140 if ((slot < 11) || (slot > 13) || pin == 0)
141 return -1;
142 if (slot == 12)
143 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
144 if (slot == 11) {
145 switch (pin) {
146 case 1: return AU1500_PCI_INTA;
147 case 2: return AU1500_PCI_INTB;
148 default: return 0xff;
149 }
150 }
151 if (slot == 13) {
152 switch (pin) {
153 case 1: return AU1500_PCI_INTA;
154 case 2: return AU1500_PCI_INTB;
155 case 3: return AU1500_PCI_INTC;
156 case 4: return AU1500_PCI_INTD;
157 }
158 }
159 return -1;
160}
161#endif
162
163#ifdef CONFIG_MIPS_MIRAGE
164static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
165{
166 if ((slot < 11) || (slot > 13) || pin == 0)
167 return -1;
168 if (slot == 11)
169 return (pin == 1) ? AU1500_PCI_INTD : 0xff;
170 if (slot == 12)
171 return (pin == 3) ? AU1500_PCI_INTC : 0xff;
172 if (slot == 13) {
173 switch (pin) {
174 case 1: return AU1500_PCI_INTA;
175 case 2: return AU1500_PCI_INTB;
176 default: return 0xff;
177 }
178 }
179 return -1;
180}
181#endif
182
183static struct resource alchemy_pci_host_res[] = {
184 [0] = {
185 .start = AU1500_PCI_PHYS_ADDR,
186 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
187 .flags = IORESOURCE_MEM,
188 },
189};
190
191static struct alchemy_pci_platdata db1xxx_pci_pd = {
192 .board_map_irq = db1xxx_map_pci_irq,
193};
194
195static struct platform_device db1xxx_pci_host_dev = {
196 .dev.platform_data = &db1xxx_pci_pd,
197 .name = "alchemy-pci",
198 .id = 0,
199 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
200 .resource = alchemy_pci_host_res,
201};
202
203static int __init db15x0_pci_init(void)
204{
205 return platform_device_register(&db1xxx_pci_host_dev);
206}
207/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
208arch_initcall(db15x0_pci_init);
209#endif
210
88static int __init db1xxx_dev_init(void) 211static int __init db1xxx_dev_init(void)
89{ 212{
90#ifdef DB1XXX_HAS_PCMCIA 213#ifdef DB1XXX_HAS_PCMCIA
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 3b4fa3206969..37c1883b5ea9 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -33,13 +33,6 @@
33 33
34#include <prom.h> 34#include <prom.h>
35 35
36
37char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
40};
41
42
43const char *get_system_type(void) 36const char *get_system_type(void)
44{ 37{
45 return "Alchemy Pb1500"; 38 return "Alchemy Pb1500";
@@ -101,20 +94,18 @@ void __init board_setup(void)
101#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 94#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
102 95
103#ifdef CONFIG_PCI 96#ifdef CONFIG_PCI
104 /* Setup PCI bus controller */ 97 {
105 au_writel(0, Au1500_PCI_CMEM); 98 void __iomem *base =
106 au_writel(0x00003fff, Au1500_CFG_BASE); 99 (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
107#if defined(__MIPSEB__) 100 /* Setup PCI bus controller */
108 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG); 101 __raw_writel(0x00003fff, base + PCI_REG_CMEM);
109#else 102 __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
110 au_writel(0xf, Au1500_PCI_CFG); 103 __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
111#endif 104 __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
112 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); 105 __raw_writel(0x00003c04, base + PCI_REG_PARAM);
113 au_writel(0, Au1500_PCI_MWBASE_REV_CCL); 106 __raw_writel(0x00000008, base + PCI_REG_MBAR);
114 au_writel(0x02a00356, Au1500_PCI_STATCMD); 107 wmb();
115 au_writel(0x00003c04, Au1500_PCI_HDRTYPE); 108 }
116 au_writel(0x00000008, Au1500_PCI_MBAR);
117 au_sync();
118#endif 109#endif
119 110
120 /* Enable sys bus clock divider when IDLE state or no bus activity. */ 111 /* Enable sys bus clock divider when IDLE state or no bus activity. */
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index 42b0e6b8cd58..9f0b5a0b4795 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -19,11 +19,56 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/platform_device.h>
22#include <asm/mach-au1x00/au1000.h> 23#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-db1x00/bcsr.h> 24#include <asm/mach-db1x00/bcsr.h>
24 25
25#include "../platform.h" 26#include "../platform.h"
26 27
28static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
29{
30 if ((slot < 12) || (slot > 13) || pin == 0)
31 return -1;
32 if (slot == 12)
33 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
34 if (slot == 13) {
35 switch (pin) {
36 case 1: return AU1500_PCI_INTA;
37 case 2: return AU1500_PCI_INTB;
38 case 3: return AU1500_PCI_INTC;
39 case 4: return AU1500_PCI_INTD;
40 }
41 }
42 return -1;
43}
44
45static struct resource alchemy_pci_host_res[] = {
46 [0] = {
47 .start = AU1500_PCI_PHYS_ADDR,
48 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
49 .flags = IORESOURCE_MEM,
50 },
51};
52
53static struct alchemy_pci_platdata pb1500_pci_pd = {
54 .board_map_irq = pb1500_map_pci_irq,
55 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
56 PCI_CONFIG_CH |
57#if defined(__MIPSEB__)
58 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
59#else
60 0,
61#endif
62};
63
64static struct platform_device pb1500_pci_host = {
65 .dev.platform_data = &pb1500_pci_pd,
66 .name = "alchemy-pci",
67 .id = 0,
68 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
69 .resource = alchemy_pci_host_res,
70};
71
27static int __init pb1500_dev_init(void) 72static int __init pb1500_dev_init(void)
28{ 73{
29 int swapped; 74 int swapped;
@@ -41,7 +86,8 @@ static int __init pb1500_dev_init(void)
41 86
42 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 87 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
43 db1x_register_norflash(64 * 1024 * 1024, 4, swapped); 88 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
89 platform_device_register(&pb1500_pci_host);
44 90
45 return 0; 91 return 0;
46} 92}
47device_initcall(pb1500_dev_init); 93arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b790213848bd..0f62d1e3df24 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -37,12 +37,6 @@
37 37
38#include <prom.h> 38#include <prom.h>
39 39
40
41char irq_tab_alchemy[][5] __initdata = {
42 [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
43 [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
44};
45
46const char *get_system_type(void) 40const char *get_system_type(void)
47{ 41{
48 return "Alchemy Pb1550"; 42 return "Alchemy Pb1550";
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index 87c79b7f3123..0c5711fa0734 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -19,13 +19,56 @@
19 */ 19 */
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22 22#include <linux/platform_device.h>
23#include <asm/mach-au1x00/au1000.h> 23#include <asm/mach-au1x00/au1000.h>
24#include <asm/mach-pb1x00/pb1550.h> 24#include <asm/mach-pb1x00/pb1550.h>
25#include <asm/mach-db1x00/bcsr.h> 25#include <asm/mach-db1x00/bcsr.h>
26 26
27#include "../platform.h" 27#include "../platform.h"
28 28
29static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
30{
31 if ((slot < 12) || (slot > 13) || pin == 0)
32 return -1;
33 if (slot == 12) {
34 switch (pin) {
35 case 1: return AU1500_PCI_INTB;
36 case 2: return AU1500_PCI_INTC;
37 case 3: return AU1500_PCI_INTD;
38 case 4: return AU1500_PCI_INTA;
39 }
40 }
41 if (slot == 13) {
42 switch (pin) {
43 case 1: return AU1500_PCI_INTA;
44 case 2: return AU1500_PCI_INTB;
45 case 3: return AU1500_PCI_INTC;
46 case 4: return AU1500_PCI_INTD;
47 }
48 }
49 return -1;
50}
51
52static struct resource alchemy_pci_host_res[] = {
53 [0] = {
54 .start = AU1500_PCI_PHYS_ADDR,
55 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
56 .flags = IORESOURCE_MEM,
57 },
58};
59
60static struct alchemy_pci_platdata pb1550_pci_pd = {
61 .board_map_irq = pb1550_map_pci_irq,
62};
63
64static struct platform_device pb1550_pci_host = {
65 .dev.platform_data = &pb1550_pci_pd,
66 .name = "alchemy-pci",
67 .id = 0,
68 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
69 .resource = alchemy_pci_host_res,
70};
71
29static int __init pb1550_dev_init(void) 72static int __init pb1550_dev_init(void)
30{ 73{
31 int swapped; 74 int swapped;
@@ -57,7 +100,8 @@ static int __init pb1550_dev_init(void)
57 100
58 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; 101 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
59 db1x_register_norflash(128 * 1024 * 1024, 4, swapped); 102 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
103 platform_device_register(&pb1550_pci_host);
60 104
61 return 0; 105 return 0;
62} 106}
63device_initcall(pb1550_dev_init); 107arch_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
index 5f8f0691ed2d..dea45c78fdcd 100644
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -36,10 +36,6 @@
36 36
37#include <prom.h> 37#include <prom.h>
38 38
39char irq_tab_alchemy[][5] __initdata = {
40 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
41};
42
43static void gpr_reset(char *c) 39static void gpr_reset(char *c)
44{ 40{
45 /* switch System-LED to orange (red# and green# on) */ 41 /* switch System-LED to orange (red# and green# on) */
@@ -76,12 +72,4 @@ void __init board_setup(void)
76 72
77 /* Take away Reset of UMTS-card */ 73 /* Take away Reset of UMTS-card */
78 alchemy_gpio_direction_output(215, 1); 74 alchemy_gpio_direction_output(215, 1);
79
80#ifdef CONFIG_PCI
81#if defined(__MIPSEB__)
82 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
83#else
84 au_writel(0xf, Au1500_PCI_CFG);
85#endif
86#endif
87} 75}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
index 14b46629cfc8..982ce85db60d 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -167,6 +167,45 @@ static struct i2c_board_info gpr_i2c_info[] __initdata = {
167 } 167 }
168}; 168};
169 169
170
171
172static struct resource alchemy_pci_host_res[] = {
173 [0] = {
174 .start = AU1500_PCI_PHYS_ADDR,
175 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
176 .flags = IORESOURCE_MEM,
177 },
178};
179
180static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
181{
182 if ((slot == 0) && (pin == 1))
183 return AU1550_PCI_INTA;
184 else if ((slot == 0) && (pin == 2))
185 return AU1550_PCI_INTB;
186
187 return -1;
188}
189
190static struct alchemy_pci_platdata gpr_pci_pd = {
191 .board_map_irq = gpr_map_pci_irq,
192 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
193 PCI_CONFIG_CH |
194#if defined(__MIPSEB__)
195 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
196#else
197 0,
198#endif
199};
200
201static struct platform_device gpr_pci_host_dev = {
202 .dev.platform_data = &gpr_pci_pd,
203 .name = "alchemy-pci",
204 .id = 0,
205 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
206 .resource = alchemy_pci_host_res,
207};
208
170static struct platform_device *gpr_devices[] __initdata = { 209static struct platform_device *gpr_devices[] __initdata = {
171 &gpr_wdt_device, 210 &gpr_wdt_device,
172 &gpr_mtd_device, 211 &gpr_mtd_device,
@@ -174,6 +213,14 @@ static struct platform_device *gpr_devices[] __initdata = {
174 &gpr_led_devices, 213 &gpr_led_devices,
175}; 214};
176 215
216static int __init gpr_pci_init(void)
217{
218 return platform_device_register(&gpr_pci_host_dev);
219}
220/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
221arch_initcall(gpr_pci_init);
222
223
177static int __init gpr_dev_init(void) 224static int __init gpr_dev_init(void)
178{ 225{
179 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info)); 226 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3ae984cf98cf..851a5ab4c8f2 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -38,20 +38,6 @@
38 38
39#include <prom.h> 39#include <prom.h>
40 40
41char irq_tab_alchemy[][5] __initdata = {
42 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
43 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
44 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
45 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
46 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
47 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
48 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
49 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
50};
51
52extern int (*board_pci_idsel)(unsigned int devsel, int assert);
53int mtx1_pci_idsel(unsigned int devsel, int assert);
54
55static void mtx1_reset(char *c) 41static void mtx1_reset(char *c)
56{ 42{
57 /* Jump to the reset vector */ 43 /* Jump to the reset vector */
@@ -74,15 +60,6 @@ void __init board_setup(void)
74 alchemy_gpio_direction_output(204, 0); 60 alchemy_gpio_direction_output(204, 0);
75#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 61#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
76 62
77#ifdef CONFIG_PCI
78#if defined(__MIPSEB__)
79 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
80#else
81 au_writel(0xf, Au1500_PCI_CFG);
82#endif
83 board_pci_idsel = mtx1_pci_idsel;
84#endif
85
86 /* Initialize sys_pinfunc */ 63 /* Initialize sys_pinfunc */
87 au_writel(SYS_PF_NI2, SYS_PINFUNC); 64 au_writel(SYS_PF_NI2, SYS_PINFUNC);
88 65
@@ -104,23 +81,6 @@ void __init board_setup(void)
104 printk(KERN_INFO "4G Systems MTX-1 Board\n"); 81 printk(KERN_INFO "4G Systems MTX-1 Board\n");
105} 82}
106 83
107int
108mtx1_pci_idsel(unsigned int devsel, int assert)
109{
110 /* This function is only necessary to support a proprietary Cardbus
111 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
112 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
113 */
114 if (assert && devsel != 0)
115 /* Suppress signal to Cardbus */
116 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
117 else
118 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
119
120 udelay(1);
121 return 1;
122}
123
124static int __init mtx1_init_irq(void) 84static int __init mtx1_init_irq(void)
125{ 85{
126 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 86 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 55628e390fd7..cc47b6868ca3 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -135,7 +135,69 @@ static struct platform_device mtx1_mtd = {
135 .resource = &mtx1_mtd_resource, 135 .resource = &mtx1_mtd_resource,
136}; 136};
137 137
138static struct resource alchemy_pci_host_res[] = {
139 [0] = {
140 .start = AU1500_PCI_PHYS_ADDR,
141 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
142 .flags = IORESOURCE_MEM,
143 },
144};
145
146static int mtx1_pci_idsel(unsigned int devsel, int assert)
147{
148 /* This function is only necessary to support a proprietary Cardbus
149 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
150 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
151 */
152 if (assert && devsel != 0)
153 /* Suppress signal to Cardbus */
154 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
155 else
156 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
157
158 udelay(1);
159 return 1;
160}
161
162static const char mtx1_irqtab[][5] = {
163 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
164 [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
165 [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
166 [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
167 [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
168 [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
169 [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
170 [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
171};
172
173static int mtx1_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
174{
175 return mtx1_irqtab[slot][pin];
176}
177
178static struct alchemy_pci_platdata mtx1_pci_pd = {
179 .board_map_irq = mtx1_map_pci_irq,
180 .board_pci_idsel = mtx1_pci_idsel,
181 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
182 PCI_CONFIG_CH |
183#if defined(__MIPSEB__)
184 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
185#else
186 0,
187#endif
188};
189
190static struct platform_device mtx1_pci_host = {
191 .dev.platform_data = &mtx1_pci_pd,
192 .name = "alchemy-pci",
193 .id = 0,
194 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
195 .resource = alchemy_pci_host_res,
196};
197
198
138static struct __initdata platform_device * mtx1_devs[] = { 199static struct __initdata platform_device * mtx1_devs[] = {
200 &mtx1_pci_host,
139 &mtx1_gpio_leds, 201 &mtx1_gpio_leds,
140 &mtx1_wdt, 202 &mtx1_wdt,
141 &mtx1_button, 203 &mtx1_button,
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 81e57fad07ab..3fa83f72e014 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -70,14 +70,6 @@ void __init board_setup(void)
70 /* Enable DTR (MCR bit 0) = USB power up */ 70 /* Enable DTR (MCR bit 0) = USB power up */
71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18)); 71 __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
72 wmb(); 72 wmb();
73
74#ifdef CONFIG_PCI
75#if defined(__MIPSEB__)
76 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
77#else
78 au_writel(0xf, Au1500_PCI_CFG);
79#endif
80#endif
81} 73}
82 74
83static int __init xxs1500_init_irq(void) 75static int __init xxs1500_init_irq(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 19:54:50 -0500