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authorManuel Lauss <manuel.lauss@googlemail.com>2009-10-15 13:07:34 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:52:55 -0500
commitb6e6d120c8dd9c9cd888645b01299e2a55d873a4 (patch)
treea4d5944980e61ec2c6819131cbb8269e340e58c1 /arch/mips/alchemy
parent8402a1588a4f63465079e98481dd83d1d9cc9a98 (diff)
MIPS: Alchemy: get rid of superfluous UART definitions
Remove unused uart bit definitions and base macros. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/platform.c44
1 files changed, 21 insertions, 23 deletions
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 5a9a4f9eba2e..195e5b3e8b41 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -20,38 +20,36 @@
20#include <asm/mach-au1x00/au1xxx_dbdma.h> 20#include <asm/mach-au1x00/au1xxx_dbdma.h>
21#include <asm/mach-au1x00/au1100_mmc.h> 21#include <asm/mach-au1x00/au1100_mmc.h>
22 22
23#define PORT(_base, _irq) \ 23#define PORT(_base, _irq) \
24 { \ 24 { \
25 .iobase = _base, \ 25 .mapbase = _base, \
26 .membase = (void __iomem *)_base,\ 26 .irq = _irq, \
27 .mapbase = CPHYSADDR(_base), \ 27 .regshift = 2, \
28 .irq = _irq, \ 28 .iotype = UPIO_AU, \
29 .regshift = 2, \ 29 .flags = UPF_SKIP_TEST | UPF_IOREMAP \
30 .iotype = UPIO_AU, \
31 .flags = UPF_SKIP_TEST \
32 } 30 }
33 31
34static struct plat_serial8250_port au1x00_uart_data[] = { 32static struct plat_serial8250_port au1x00_uart_data[] = {
35#if defined(CONFIG_SERIAL_8250_AU1X00) 33#if defined(CONFIG_SERIAL_8250_AU1X00)
36#if defined(CONFIG_SOC_AU1000) 34#if defined(CONFIG_SOC_AU1000)
37 PORT(UART0_ADDR, AU1000_UART0_INT), 35 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
38 PORT(UART1_ADDR, AU1000_UART1_INT), 36 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
39 PORT(UART2_ADDR, AU1000_UART2_INT), 37 PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),
40 PORT(UART3_ADDR, AU1000_UART3_INT), 38 PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),
41#elif defined(CONFIG_SOC_AU1500) 39#elif defined(CONFIG_SOC_AU1500)
42 PORT(UART0_ADDR, AU1500_UART0_INT), 40 PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),
43 PORT(UART3_ADDR, AU1500_UART3_INT), 41 PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),
44#elif defined(CONFIG_SOC_AU1100) 42#elif defined(CONFIG_SOC_AU1100)
45 PORT(UART0_ADDR, AU1100_UART0_INT), 43 PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),
46 PORT(UART1_ADDR, AU1100_UART1_INT), 44 PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),
47 PORT(UART3_ADDR, AU1100_UART3_INT), 45 PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),
48#elif defined(CONFIG_SOC_AU1550) 46#elif defined(CONFIG_SOC_AU1550)
49 PORT(UART0_ADDR, AU1550_UART0_INT), 47 PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),
50 PORT(UART1_ADDR, AU1550_UART1_INT), 48 PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),
51 PORT(UART3_ADDR, AU1550_UART3_INT), 49 PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),
52#elif defined(CONFIG_SOC_AU1200) 50#elif defined(CONFIG_SOC_AU1200)
53 PORT(UART0_ADDR, AU1200_UART0_INT), 51 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
54 PORT(UART1_ADDR, AU1200_UART1_INT), 52 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
55#endif 53#endif
56#endif /* CONFIG_SERIAL_8250_AU1X00 */ 54#endif /* CONFIG_SERIAL_8250_AU1X00 */
57 { }, 55 { },