MIPS: Alchemy: Au1300 SoC support

Add basic support for the Au1300 variant(s):
- New GPIO/Interrupt controller
- DBDMA ids
- USB setup
- MMC support
- enable various PSC drivers
- detection code.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2866/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

10 files changed, 695 insertions, 3 deletions

diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 36df5e2c8e07..766badaef3b0 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -2,6 +2,10 @@
 config ALCHEMY_GPIOINT_AU1000
         bool
 
+# au1300-style GPIO/INT controller
+config ALCHEMY_GPIOINT_AU1300
+        bool
+
 # select this in your board config if you don't want to use the gpio
 # namespace as documented in the manuals.  In this case however you need
 # to create the necessary gpio_* functions in your board code/headers!
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 811ece7b22e3..d3f5c5137804 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,9 +6,10 @@
 #
 
 obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
-        sleeper.o dma.o dbdma.o
+        sleeper.o dma.o dbdma.o vss.o
 
 obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
+obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o
 
 # optional gpiolib support
 ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 0e63ee487d6d..c723ec1d3b2c 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
         { DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 };
 
+static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
+        { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8,  0x10100004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8,  0x10100000, 0, 0 },
+        { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8,  0x10101004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN,  0, 8,  0x10101000, 0, 0 },
+        { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8,  0x10102004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN,  0, 8,  0x10102000, 0, 0 },
+        { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8,  0x10103004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN,  0, 8,  0x10103000, 0, 0 },
+
+        { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8,  0x10600000, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN,  4, 8,  0x10600004, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8,  0x10601000, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN,  8, 8,  0x10601004, 0, 0 },
+
+        { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN ,   4, 32, 0x10300008, 0, 0 },
+        { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT,   4, 32, 0x10300004, 0, 0 },
+
+        { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0001c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN,   0, 16, 0x10a0001c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0101c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN,   0, 16, 0x10a0101c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0201c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN,   0, 16, 0x10a0201c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0301c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN,   0, 16, 0x10a0301c, 0, 0 },
+
+        { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE,   0, 0,  0x00000000, 0, 0 },
+        { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+
+        { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8,  0x10602000, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN,  4, 8,  0x10602004, 0, 0 },
+
+        { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+        { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE,  0, 32, 0x14001810, 0, 0 },
+
+        { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+        { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+
+        { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+        { DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+};
+
 /* 32 predefined plus 32 custom */
 #define DBDEV_TAB_SIZE          64
 
@@ -1038,6 +1082,8 @@ static int __init alchemy_dbdma_init(void)
                 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
         case ALCHEMY_CPU_AU1200:
                 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
+        case ALCHEMY_CPU_AU1300:
+                return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
         }
         return 0;
 }
diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c
new file mode 100644
index 000000000000..b8cd3364ff69
--- /dev/null
+++ b/arch/mips/alchemy/common/gpioint.c
@@ -0,0 +1,411 @@
+/*
+ * gpioint.c - Au1300 GPIO+Interrupt controller (I call it "GPIC") support.
+ *
+ * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
+ *
+ * licensed under the GPLv2.
+ */
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/syscore_ops.h>
+#include <linux/types.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/gpio-au1300.h>
+
+static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
+
+/* setup for known onchip sources */
+struct gpic_devint_data {
+        int irq;        /* linux IRQ number */
+        int type;       /* IRQ_TYPE_ */
+        int prio;       /* irq priority, 0 highest, 3 lowest */
+        int internal;   /* internal source (no ext. pin)? */
+};
+
+static const struct gpic_devint_data au1300_devints[] __initdata = {
+        /* multifunction: gpio pin or device */
+        { AU1300_UART1_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_UART2_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_UART3_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_SD1_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_SD2_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC0_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC1_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC2_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC3_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_NAND_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        /* au1300 internal */
+        { AU1300_DDMA_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_MMU_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_MPU_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_GPU_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_UDMA_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_TOY_INT,        IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_INT,        IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING,  0, 1, },
+        { AU1300_UART0_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_SD0_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_USB_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_LCD_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_BSA_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_MPE_INT,        IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_ITE_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_AES_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_CIM_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { -1, },        /* terminator */
+};
+
+
+/*
+ * au1300_gpic_chgcfg - change PIN configuration.
+ * @gpio:       pin to change (0-based GPIO number from datasheet).
+ * @clr:        clear all bits set in 'clr'.
+ * @set:        set these bits.
+ *
+ * modifies a pins' configuration register, bits set in @clr will
+ * be cleared in the register, bits in @set will be set.
+ */
+static inline void au1300_gpic_chgcfg(unsigned int gpio,
+                                      unsigned long clr,
+                                      unsigned long set)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long l;
+
+        r += gpio * 4;  /* offset into pin config array */
+        l = __raw_readl(r + AU1300_GPIC_PINCFG);
+        l &= ~clr;
+        l |= set;
+        __raw_writel(l, r + AU1300_GPIC_PINCFG);
+        wmb();
+}
+
+/*
+ * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl).
+ * @pin:        pin (0-based GPIO number from datasheet).
+ *
+ * Assigns a GPIO pin to the GPIO controller, so its level can either
+ * be read or set through the generic GPIO functions.
+ * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1).
+ * REVISIT: is this function really necessary?
+ */
+void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio)
+{
+        au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE);
+}
+EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio);
+
+/*
+ * au1300_pinfunc_to_dev - assign a pin to the device function.
+ * @pin:        pin (0-based GPIO number from datasheet).
+ *
+ * Assigns a GPIO pin to its associated device function; the pin will be
+ * driven by the device and not through GPIO functions.
+ */
+void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        r += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, r + AU1300_GPIC_DEVSEL);
+        wmb();
+}
+EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev);
+
+/*
+ * au1300_set_irq_priority -  set internal priority of IRQ.
+ * @irq:        irq to set priority (linux irq number).
+ * @p:          priority (0 = highest, 3 = lowest).
+ */
+void au1300_set_irq_priority(unsigned int irq, int p)
+{
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p));
+}
+EXPORT_SYMBOL_GPL(au1300_set_irq_priority);
+
+/*
+ * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers.
+ * @dchan:      dbdma trigger select (0, 1).
+ * @gpio:       pin to assign as trigger.
+ *
+ * DBDMA controller has 2 external trigger sources; this function
+ * assigns a GPIO to the selected trigger.
+ */
+void au1300_set_dbdma_gpio(int dchan, unsigned int gpio)
+{
+        unsigned long r;
+
+        if ((dchan >= 0) && (dchan <= 1)) {
+                r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
+                r &= ~(0xff << (8 * dchan));
+                r |= (gpio & 0x7f) << (8 * dchan);
+                __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
+                wmb();
+        }
+}
+
+/**********************************************************************/
+
+static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow)
+{
+        au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE,
+                           allow ? GPIC_CFG_IDLEWAKE : 0);
+}
+
+static void au1300_gpic_mask(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IDIS);
+        wmb();
+
+        gpic_pin_set_idlewake(irq, 0);
+}
+
+static void au1300_gpic_unmask(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+
+        gpic_pin_set_idlewake(irq, 1);
+
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IEN);
+        wmb();
+}
+
+static void au1300_gpic_maskack(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IPEND);       /* ack */
+        __raw_writel(bit, r + AU1300_GPIC_IDIS);        /* mask */
+        wmb();
+
+        gpic_pin_set_idlewake(irq, 0);
+}
+
+static void au1300_gpic_ack(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IPEND);       /* ack */
+        wmb();
+}
+
+static struct irq_chip au1300_gpic = {
+        .name           = "GPIOINT",
+        .irq_ack        = au1300_gpic_ack,
+        .irq_mask       = au1300_gpic_mask,
+        .irq_mask_ack   = au1300_gpic_maskack,
+        .irq_unmask     = au1300_gpic_unmask,
+        .irq_set_type   = au1300_gpic_settype,
+};
+
+static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
+{
+        unsigned long s;
+        unsigned char *name = NULL;
+        irq_flow_handler_t hdl = NULL;
+
+        switch (type) {
+        case IRQ_TYPE_LEVEL_HIGH:
+                s = GPIC_CFG_IC_LEVEL_HIGH;
+                name = "high";
+                hdl = handle_level_irq;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                s = GPIC_CFG_IC_LEVEL_LOW;
+                name = "low";
+                hdl = handle_level_irq;
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                s = GPIC_CFG_IC_EDGE_RISE;
+                name = "posedge";
+                hdl = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                s = GPIC_CFG_IC_EDGE_FALL;
+                name = "negedge";
+                hdl = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                s = GPIC_CFG_IC_EDGE_BOTH;
+                name = "bothedge";
+                hdl = handle_edge_irq;
+                break;
+        case IRQ_TYPE_NONE:
+                s = GPIC_CFG_IC_OFF;
+                name = "disabled";
+                hdl = handle_level_irq;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name);
+
+        au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);
+
+        return 0;
+}
+
+static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints)
+{
+        int i;
+        void __iomem *bank_base;
+
+        mips_cpu_irq_init();
+
+        /* disable & ack all possible interrupt sources */
+        for (i = 0; i < 4; i++) {
+                bank_base = AU1300_GPIC_ADDR + (i * 4);
+                __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
+                wmb();
+                __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
+                wmb();
+        }
+
+        /* register an irq_chip for them, with 2nd highest priority */
+        for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {
+                au1300_set_irq_priority(i, 1);
+                au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
+        }
+
+        /* setup known on-chip sources */
+        while ((i = dints->irq) != -1) {
+                au1300_gpic_settype(irq_get_irq_data(i), dints->type);
+                au1300_set_irq_priority(i, dints->prio);
+
+                if (dints->internal)
+                        au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);
+
+                dints++;
+        }
+
+        set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
+}
+
+static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
+
+static int alchemy_gpic_suspend(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
+        int i;
+
+        /* save 4 interrupt mask status registers */
+        alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
+        alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
+        alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
+        alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
+
+        /* save misc register(s) */
+        alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
+
+        /* molto silenzioso */
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
+        wmb();
+
+        /* save pin/int-type configuration */
+        base += AU1300_GPIC_PINCFG;
+        for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
+                alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
+
+        wmb();
+
+        return 0;
+}
+
+static void alchemy_gpic_resume(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
+        int i;
+
+        /* disable all first */
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
+        wmb();
+
+        /* restore pin/int-type configurations */
+        base += AU1300_GPIC_PINCFG;
+        for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
+                __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
+        wmb();
+
+        /* restore misc register(s) */
+        base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
+        __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
+        wmb();
+
+        /* finally restore masks */
+        __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
+        __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
+        __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
+        __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
+        wmb();
+}
+
+static struct syscore_ops alchemy_gpic_pmops = {
+        .suspend        = alchemy_gpic_suspend,
+        .resume         = alchemy_gpic_resume,
+};
+
+/**********************************************************************/
+
+void __init arch_init_irq(void)
+{
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1300:
+                alchemy_gpic_init_irq(&au1300_devints[0]);
+                register_syscore_ops(&alchemy_gpic_pmops);
+                break;
+        }
+}
+
+#define CAUSEF_GPIC (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5)
+
+void plat_irq_dispatch(void)
+{
+        unsigned long i, c = read_c0_cause() & read_c0_status();
+
+        if (c & CAUSEF_IP7)                             /* c0 timer */
+                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
+        else if (likely(c & CAUSEF_GPIC)) {
+                i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
+                do_IRQ(i + ALCHEMY_GPIC_INT_BASE);
+        } else
+                spurious_interrupt();
+}
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 91fb4d9e30fd..f1b50f0c01db 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -27,6 +27,7 @@
  *       CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
  *      au1000 SoC have only one GPIO block : GPIO1
  *      Au1100, Au15x0, Au12x0 have a second one : GPIO2
+ *      Au1300 is totally different: 1 block with up to 128 GPIOs
  */
 
 #include <linux/init.h>
@@ -35,6 +36,7 @@
 #include <linux/types.h>
 #include <linux/gpio.h>
 #include <asm/mach-au1x00/gpio-au1000.h>
+#include <asm/mach-au1x00/gpio-au1300.h>
 
 static int gpio2_get(struct gpio_chip *chip, unsigned offset)
 {
@@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = {
         },
 };
 
+static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
+{
+        return au1300_gpio_get_value(off + AU1300_GPIO_BASE);
+}
+
+static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
+{
+        au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
+}
+
+static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
+{
+        return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
+}
+
+static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
+                                   int v)
+{
+        return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
+}
+
+static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
+{
+        return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
+}
+
+static struct gpio_chip au1300_gpiochip = {
+        .label                  = "alchemy-gpic",
+        .direction_input        = alchemy_gpic_dir_input,
+        .direction_output       = alchemy_gpic_dir_output,
+        .get                    = alchemy_gpic_get,
+        .set                    = alchemy_gpic_set,
+        .to_irq                 = alchemy_gpic_gpio_to_irq,
+        .base                   = AU1300_GPIO_BASE,
+        .ngpio                  = AU1300_GPIO_NUM,
+};
+
 static int __init alchemy_gpiochip_init(void)
 {
         int ret = 0;
@@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void)
                 ret = gpiochip_add(&alchemy_gpio_chip[0]);
                 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                ret = gpiochip_add(&au1300_gpiochip);
+                break;
         }
         return ret;
 }
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index c8e5d72a5826..95cb9113b12c 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
                 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
                 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
         },
+        [ALCHEMY_CPU_AU1300] = {
+                PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
+                PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
+                PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
+                PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
+        },
 };
 
 static struct platform_device au1xx0_uart_device = {
@@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = {
         [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
         [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
         [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
+        [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
 };
 
 static unsigned long alchemy_ehci_data[][2] __initdata = {
         [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
+        [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
 };
 
 static int __init _new_usbres(struct resource **r, struct platform_device **d)
@@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype)
                 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
 
 
-        /* setup EHCI0: Au1200 */
-        if (ctype == ALCHEMY_CPU_AU1200) {
+        /* setup EHCI0: Au1200/Au1300 */
+        if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
                 if (_new_usbres(&res, &pdev))
                         return;
 
@@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype)
                 if (platform_device_register(pdev))
                         printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
         }
+
+        /* Au1300: OHCI1 */
+        if (ctype == ALCHEMY_CPU_AU1300) {
+                if (_new_usbres(&res, &pdev))
+                        return;
+
+                res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
+                res[0].end = res[0].start + 0x100 - 1;
+                res[0].flags = IORESOURCE_MEM;
+                res[1].start = AU1300_USB_INT;
+                res[1].end = res[1].start;
+                res[1].flags = IORESOURCE_IRQ;
+                pdev->name = "au1xxx-ohci";
+                pdev->id = 1;
+                pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+
+                if (platform_device_register(pdev))
+                        printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
+        }
 }
 
 /* Macro to help defining the Ethernet MAC resources */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bdd6651e9a4f..0c7fce2a3c12 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -126,6 +126,9 @@ void au_sleep(void)
         case ALCHEMY_CPU_AU1200:
                 alchemy_sleep_au1550();
                 break;
+        case ALCHEMY_CPU_AU1300:
+                alchemy_sleep_au1300();
+                break;
         }
 
         restore_core_regs();
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 77f3c743b716..c7bcc7e5c822 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550)
 
 END(alchemy_sleep_au1550)
 
+/* sleepcode for Au1300 memory controller type */
+LEAF(alchemy_sleep_au1300)
+
+        SETUP_SLEEP
+
+        /* cache following instructions, as memory gets put to sleep */
+        la      t0, 2f
+        la      t1, 4f
+        subu    t2, t1, t0
+
+        .set    mips3
+
+1:      cache   0x14, 0(t0)
+        subu    t2, t2, 32
+        bgez    t2, 1b
+         addu   t0, t0, 32
+
+        .set    mips0
+
+2:      lui     a0, 0xb400              /* mem_xxx */
+
+        /* disable all ports in mem_sdportcfga */
+        sw      zero, 0x868(a0)         /* mem_sdportcfga */
+        sync
+
+        /* disable ODT */
+        li      t0, 0x03010000
+        sw      t0, 0x08d8(a0)          /* mem_sdcmd0 */
+        sw      t0, 0x08dc(a0)          /* mem_sdcmd1 */
+        sync
+
+        /* precharge */
+        li      t0, 0x23000400
+        sw      t0, 0x08dc(a0)          /* mem_sdcmd1 */
+        sw      t0, 0x08d8(a0)          /* mem_sdcmd0 */
+        sync
+
+        /* auto refresh */
+        sw      zero, 0x08c8(a0)        /* mem_sdautoref */
+        sync
+
+        /* block access to the DDR */
+        lw      t0, 0x0848(a0)          /* mem_sdconfigb */
+        li      t1, (1 << 7 | 0x3F)
+        or      t0, t0, t1
+        sw      t0, 0x0848(a0)          /* mem_sdconfigb */
+        sync
+
+        /* issue the Self Refresh command */
+        li      t0, 0x10000000
+        sw      t0, 0x08dc(a0)          /* mem_sdcmd1 */
+        sw      t0, 0x08d8(a0)          /* mem_sdcmd0 */
+        sync
+
+        /* wait for sdram to enter self-refresh mode */
+        lui     t0, 0x0300
+3:      lw      t1, 0x0850(a0)          /* mem_sdstat */
+        and     t2, t1, t0
+        bne     t2, t0, 3b
+         nop
+
+        /* disable SDRAM clocks */
+        li      t0, ~(3<<28)
+        lw      t1, 0x0840(a0)          /* mem_sdconfiga */
+        and     t1, t1, t0              /* clear CE[1:0] */
+        sw      t1, 0x0840(a0)          /* mem_sdconfiga */
+        sync
+
+        DO_SLEEP
+4:
+
+END(alchemy_sleep_au1300)
+
 
         /* This is where we return upon wakeup.
          * Reload all of the registers and return.
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index d5da6adbf634..a594a85337d6 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = {
         AU1100_RTC_MATCH2_INT,
         AU1550_RTC_MATCH2_INT,
         AU1200_RTC_MATCH2_INT,
+        AU1300_RTC_MATCH2_INT,
 };
 
 void __init plat_time_init(void)
diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c
new file mode 100644
index 000000000000..d23b1444d365
--- /dev/null
+++ b/arch/mips/alchemy/common/vss.c
@@ -0,0 +1,84 @@
+/*
+ * Au1300 media block power gating (VSS)
+ *
+ * This is a stop-gap solution until I have the clock framework integration
+ * ready. This stuff here really must be handled transparently when clocks
+ * for various media blocks are enabled/disabled.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#define VSS_GATE        0x00    /* gate wait timers */
+#define VSS_CLKRST      0x04    /* clock/block control */
+#define VSS_FTR         0x08    /* footers */
+
+#define VSS_ADDR(blk)   (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
+
+static DEFINE_SPINLOCK(au1300_vss_lock);
+
+/* enable a block as outlined in the databook */
+static inline void __enable_block(int block)
+{
+        void __iomem *base = (void __iomem *)VSS_ADDR(block);
+
+        __raw_writel(3, base + VSS_CLKRST);     /* enable clock, assert reset */
+        wmb();
+
+        __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
+        wmb();
+
+        /* enable footers in sequence */
+        __raw_writel(0x01, base + VSS_FTR);
+        wmb();
+        __raw_writel(0x03, base + VSS_FTR);
+        wmb();
+        __raw_writel(0x07, base + VSS_FTR);
+        wmb();
+        __raw_writel(0x0f, base + VSS_FTR);
+        wmb();
+
+        __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
+        wmb();
+
+        __raw_writel(2, base + VSS_CLKRST);     /* deassert reset */
+        wmb();
+
+        __raw_writel(0x1f, base + VSS_FTR);     /* enable isolation cells */
+        wmb();
+}
+
+/* disable a block as outlined in the databook */
+static inline void __disable_block(int block)
+{
+        void __iomem *base = (void __iomem *)VSS_ADDR(block);
+
+        __raw_writel(0x0f, base + VSS_FTR);     /* disable isolation cells */
+        wmb();
+        __raw_writel(0, base + VSS_GATE);       /* disable FSM */
+        wmb();
+        __raw_writel(3, base + VSS_CLKRST);     /* assert reset */
+        wmb();
+        __raw_writel(1, base + VSS_CLKRST);     /* disable clock */
+        wmb();
+        __raw_writel(0, base + VSS_FTR);        /* disable all footers */
+        wmb();
+}
+
+void au1300_vss_block_control(int block, int enable)
+{
+        unsigned long flags;
+
+        if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300)
+                return;
+
+        /* only one block at a time */
+        spin_lock_irqsave(&au1300_vss_lock, flags);
+        if (enable)
+                __enable_block(block);
+        else
+                __disable_block(block);
+        spin_unlock_irqrestore(&au1300_vss_lock, flags);
+}
+EXPORT_SYMBOL_GPL(au1300_vss_block_control);