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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/alchemy
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/Platform6
-rw-r--r--arch/mips/alchemy/board-gpr.c12
-rw-r--r--arch/mips/alchemy/board-mtx1.c8
-rw-r--r--arch/mips/alchemy/common/dbdma.c14
-rw-r--r--arch/mips/alchemy/common/gpiolib.c14
-rw-r--r--arch/mips/alchemy/common/irq.c178
-rw-r--r--arch/mips/alchemy/common/platform.c4
-rw-r--r--arch/mips/alchemy/common/setup.c2
-rw-r--r--arch/mips/alchemy/common/sleeper.S20
-rw-r--r--arch/mips/alchemy/common/time.c2
-rw-r--r--arch/mips/alchemy/common/usb.c2
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c2
-rw-r--r--arch/mips/alchemy/devboards/db1000.c16
-rw-r--r--arch/mips/alchemy/devboards/db1200.c28
-rw-r--r--arch/mips/alchemy/devboards/db1300.c10
-rw-r--r--arch/mips/alchemy/devboards/db1550.c18
-rw-r--r--arch/mips/alchemy/devboards/pm.c2
17 files changed, 169 insertions, 169 deletions
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 942c5800a684..fa1bdd1aea15 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -1,7 +1,7 @@
1# 1#
2# Core Alchemy code 2# Core Alchemy code
3# 3#
4platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/ 4platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
5 5
6 6
7# 7#
@@ -45,7 +45,7 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
45# 45#
46# MyCable eval board 46# MyCable eval board
47# 47#
48platform-$(CONFIG_MIPS_XXS1500) += alchemy/ 48platform-$(CONFIG_MIPS_XXS1500) += alchemy/
49load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 49load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
50 50
51# 51#
@@ -56,7 +56,7 @@ load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
56 56
57# boards can specify their own <gpio.h> in one of their include dirs. 57# boards can specify their own <gpio.h> in one of their include dirs.
58# If they do, placing this line here at the end will make sure the 58# If they do, placing this line here at the end will make sure the
59# compiler picks the board one. If they don't, it will make sure 59# compiler picks the board one. If they don't, it will make sure
60# the alchemy generic gpio header is picked up. 60# the alchemy generic gpio header is picked up.
61 61
62cflags-$(CONFIG_MIPS_ALCHEMY) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 62cflags-$(CONFIG_MIPS_ALCHEMY) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index ba3259086b9d..cb0f6afb7389 100644
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -135,33 +135,33 @@ static struct mtd_partition gpr_mtd_partitions[] = {
135 { 135 {
136 .name = "kernel", 136 .name = "kernel",
137 .size = 0x00200000, 137 .size = 0x00200000,
138 .offset = 0, 138 .offset = 0,
139 }, 139 },
140 { 140 {
141 .name = "rootfs", 141 .name = "rootfs",
142 .size = 0x00800000, 142 .size = 0x00800000,
143 .offset = MTDPART_OFS_APPEND, 143 .offset = MTDPART_OFS_APPEND,
144 .mask_flags = MTD_WRITEABLE, 144 .mask_flags = MTD_WRITEABLE,
145 }, 145 },
146 { 146 {
147 .name = "config", 147 .name = "config",
148 .size = 0x00200000, 148 .size = 0x00200000,
149 .offset = 0x01d00000, 149 .offset = 0x01d00000,
150 }, 150 },
151 { 151 {
152 .name = "yamon", 152 .name = "yamon",
153 .size = 0x00100000, 153 .size = 0x00100000,
154 .offset = 0x01c00000, 154 .offset = 0x01c00000,
155 }, 155 },
156 { 156 {
157 .name = "yamon env vars", 157 .name = "yamon env vars",
158 .size = 0x00040000, 158 .size = 0x00040000,
159 .offset = MTDPART_OFS_APPEND, 159 .offset = MTDPART_OFS_APPEND,
160 }, 160 },
161 { 161 {
162 .name = "kernel+rootfs", 162 .name = "kernel+rootfs",
163 .size = 0x00a00000, 163 .size = 0x00a00000,
164 .offset = 0, 164 .offset = 0,
165 }, 165 },
166}; 166};
167 167
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index a124c251c0c9..4a9baa9f6330 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -173,23 +173,23 @@ static struct mtd_partition mtx1_mtd_partitions[] = {
173 { 173 {
174 .name = "filesystem", 174 .name = "filesystem",
175 .size = 0x01C00000, 175 .size = 0x01C00000,
176 .offset = 0, 176 .offset = 0,
177 }, 177 },
178 { 178 {
179 .name = "yamon", 179 .name = "yamon",
180 .size = 0x00100000, 180 .size = 0x00100000,
181 .offset = MTDPART_OFS_APPEND, 181 .offset = MTDPART_OFS_APPEND,
182 .mask_flags = MTD_WRITEABLE, 182 .mask_flags = MTD_WRITEABLE,
183 }, 183 },
184 { 184 {
185 .name = "kernel", 185 .name = "kernel",
186 .size = 0x002c0000, 186 .size = 0x002c0000,
187 .offset = MTDPART_OFS_APPEND, 187 .offset = MTDPART_OFS_APPEND,
188 }, 188 },
189 { 189 {
190 .name = "yamon env", 190 .name = "yamon env",
191 .size = 0x00040000, 191 .size = 0x00040000,
192 .offset = MTDPART_OFS_APPEND, 192 .offset = MTDPART_OFS_APPEND,
193 }, 193 },
194}; 194};
195 195
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index cf02d7dc2df0..19d5642c16d9 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -252,7 +252,7 @@ EXPORT_SYMBOL(au1xxx_ddma_del_device);
252u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 252u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
253 void (*callback)(int, void *), void *callparam) 253 void (*callback)(int, void *), void *callparam)
254{ 254{
255 unsigned long flags; 255 unsigned long flags;
256 u32 used, chan; 256 u32 used, chan;
257 u32 dcp; 257 u32 dcp;
258 int i; 258 int i;
@@ -512,7 +512,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
512 break; 512 break;
513 } 513 }
514 514
515 /* If source input is FIFO, set static address. */ 515 /* If source input is FIFO, set static address. */
516 if (stp->dev_flags & DEV_FLAGS_IN) { 516 if (stp->dev_flags & DEV_FLAGS_IN) {
517 if (stp->dev_flags & DEV_FLAGS_BURSTABLE) 517 if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
518 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); 518 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
@@ -635,7 +635,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
636 ctp->chan_ptr->ddma_dbell = 0; 636 ctp->chan_ptr->ddma_dbell = 0;
637 637
638 /* Get next descriptor pointer. */ 638 /* Get next descriptor pointer. */
639 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 639 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
640 640
641 /* Return something non-zero. */ 641 /* Return something non-zero. */
@@ -697,7 +697,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
698 ctp->chan_ptr->ddma_dbell = 0; 698 ctp->chan_ptr->ddma_dbell = 0;
699 699
700 /* Get next descriptor pointer. */ 700 /* Get next descriptor pointer. */
701 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 701 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
702 702
703 /* Return something non-zero. */ 703 /* Return something non-zero. */
@@ -742,7 +742,7 @@ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
742 *nbytes = dp->dscr_cmd1; 742 *nbytes = dp->dscr_cmd1;
743 rv = dp->dscr_stat; 743 rv = dp->dscr_stat;
744 744
745 /* Get next descriptor pointer. */ 745 /* Get next descriptor pointer. */
746 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 746 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
747 747
748 /* Return something non-zero. */ 748 /* Return something non-zero. */
@@ -891,7 +891,7 @@ void au1xxx_dbdma_dump(u32 chanid)
891 chan_tab_t *ctp; 891 chan_tab_t *ctp;
892 au1x_ddma_desc_t *dp; 892 au1x_ddma_desc_t *dp;
893 dbdev_tab_t *stp, *dtp; 893 dbdev_tab_t *stp, *dtp;
894 au1x_dma_chan_t *cp; 894 au1x_dma_chan_t *cp;
895 u32 i = 0; 895 u32 i = 0;
896 896
897 ctp = *((chan_tab_t **)chanid); 897 ctp = *((chan_tab_t **)chanid);
@@ -969,7 +969,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
969 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; 969 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
970 ctp->chan_ptr->ddma_dbell = 0; 970 ctp->chan_ptr->ddma_dbell = 0;
971 971
972 /* Get next descriptor pointer. */ 972 /* Get next descriptor pointer. */
973 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); 973 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
974 974
975 /* Return something non-zero. */ 975 /* Return something non-zero. */
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index f1b50f0c01db..f9bc4f520440 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -106,14 +106,14 @@ struct gpio_chip alchemy_gpio_chip[] = {
106 .ngpio = ALCHEMY_GPIO1_NUM, 106 .ngpio = ALCHEMY_GPIO1_NUM,
107 }, 107 },
108 [1] = { 108 [1] = {
109 .label = "alchemy-gpio2", 109 .label = "alchemy-gpio2",
110 .direction_input = gpio2_direction_input, 110 .direction_input = gpio2_direction_input,
111 .direction_output = gpio2_direction_output, 111 .direction_output = gpio2_direction_output,
112 .get = gpio2_get, 112 .get = gpio2_get,
113 .set = gpio2_set, 113 .set = gpio2_set,
114 .to_irq = gpio2_to_irq, 114 .to_irq = gpio2_to_irq,
115 .base = ALCHEMY_GPIO2_BASE, 115 .base = ALCHEMY_GPIO2_BASE,
116 .ngpio = ALCHEMY_GPIO2_NUM, 116 .ngpio = ALCHEMY_GPIO2_NUM,
117 }, 117 },
118}; 118};
119 119
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 94fbcd19eb9c..63a71817a00c 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -84,20 +84,20 @@ static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
84 * needs the highest priority. 84 * needs the highest priority.
85 */ 85 */
86struct alchemy_irqmap au1000_irqmap[] __initdata = { 86struct alchemy_irqmap au1000_irqmap[] __initdata = {
87 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 87 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
88 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 88 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
89 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 89 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
90 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 90 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
91 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 91 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
92 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 92 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
93 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 93 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
94 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 94 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
95 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 95 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
96 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 96 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
97 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 97 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
98 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 98 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
99 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 99 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
100 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 100 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
101 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 101 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
102 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 102 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
103 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 103 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
@@ -106,33 +106,33 @@ struct alchemy_irqmap au1000_irqmap[] __initdata = {
106 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 106 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
107 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 107 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
108 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, 108 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
109 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 109 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
110 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 110 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
111 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, 111 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
112 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 112 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
113 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 113 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
114 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 114 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
115 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 115 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
116 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 116 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
117 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 117 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
118 { -1, }, 118 { -1, },
119}; 119};
120 120
121struct alchemy_irqmap au1500_irqmap[] __initdata = { 121struct alchemy_irqmap au1500_irqmap[] __initdata = {
122 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 122 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
123 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 123 { AU1500_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 },
124 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 124 { AU1500_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 },
125 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 125 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
126 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 126 { AU1500_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 },
127 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 127 { AU1500_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 },
128 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 128 { AU1500_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
129 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 129 { AU1500_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
130 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 130 { AU1500_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
131 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 131 { AU1500_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
132 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 132 { AU1500_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
133 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 133 { AU1500_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
134 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 134 { AU1500_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
135 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 135 { AU1500_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
136 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 136 { AU1500_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
137 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 137 { AU1500_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
138 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 138 { AU1500_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
@@ -141,31 +141,31 @@ struct alchemy_irqmap au1500_irqmap[] __initdata = {
141 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 141 { AU1500_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
142 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 142 { AU1500_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
143 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, 143 { AU1500_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
144 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, 144 { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
145 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 145 { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
146 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 146 { AU1500_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
147 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 147 { AU1500_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
148 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 148 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
149 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 149 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
150 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 150 { AU1500_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
151 { -1, }, 151 { -1, },
152}; 152};
153 153
154struct alchemy_irqmap au1100_irqmap[] __initdata = { 154struct alchemy_irqmap au1100_irqmap[] __initdata = {
155 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 155 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
156 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 156 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
157 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 157 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
158 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 158 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
159 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 159 { AU1100_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
160 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 160 { AU1100_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
161 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 161 { AU1100_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
162 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 162 { AU1100_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
163 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 163 { AU1100_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
164 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 164 { AU1100_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
165 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 165 { AU1100_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
166 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 166 { AU1100_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
167 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 167 { AU1100_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
168 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 168 { AU1100_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
169 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 169 { AU1100_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
170 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 170 { AU1100_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
171 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 171 { AU1100_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
@@ -174,33 +174,33 @@ struct alchemy_irqmap au1100_irqmap[] __initdata = {
174 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 174 { AU1100_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
175 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 175 { AU1100_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
176 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, 176 { AU1100_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
177 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 177 { AU1100_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
178 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 178 { AU1100_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
179 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, 179 { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
180 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 180 { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
181 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 181 { AU1100_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
182 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 182 { AU1100_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
183 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 183 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
184 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 184 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
185 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 185 { AU1100_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
186 { -1, }, 186 { -1, },
187}; 187};
188 188
189struct alchemy_irqmap au1550_irqmap[] __initdata = { 189struct alchemy_irqmap au1550_irqmap[] __initdata = {
190 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 190 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
191 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 191 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1, 0 },
192 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 192 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1, 0 },
193 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 193 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
194 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 194 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
195 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 195 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1, 0 },
196 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 196 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1, 0 },
197 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 197 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
198 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 198 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
199 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 199 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
200 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 200 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
201 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 201 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
202 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 202 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
203 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 203 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
204 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 204 { AU1550_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
205 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 205 { AU1550_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
206 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 206 { AU1550_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
@@ -210,26 +210,26 @@ struct alchemy_irqmap au1550_irqmap[] __initdata = {
210 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 210 { AU1550_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
211 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, 211 { AU1550_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
212 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 212 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
213 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 }, 213 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0, 0 },
214 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 214 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
215 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 }, 215 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1, 0 },
216 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 216 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
217 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 217 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
218 { -1, }, 218 { -1, },
219}; 219};
220 220
221struct alchemy_irqmap au1200_irqmap[] __initdata = { 221struct alchemy_irqmap au1200_irqmap[] __initdata = {
222 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 222 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
223 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 223 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
224 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 224 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
225 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 225 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
226 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 226 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
227 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 227 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
228 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 228 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
229 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 229 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
230 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 230 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
231 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 231 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
232 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 232 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
233 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 233 { AU1200_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
234 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 234 { AU1200_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
235 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 235 { AU1200_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
@@ -239,9 +239,9 @@ struct alchemy_irqmap au1200_irqmap[] __initdata = {
239 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 239 { AU1200_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
240 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 }, 240 { AU1200_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 0 },
241 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 }, 241 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
242 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 242 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
243 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 243 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
244 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 }, 244 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0 },
245 { -1, }, 245 { -1, },
246}; 246};
247 247
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 7af941d8e717..9837a134a6d6 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -53,7 +53,7 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
53 .irq = _irq, \ 53 .irq = _irq, \
54 .regshift = 2, \ 54 .regshift = 2, \
55 .iotype = UPIO_AU, \ 55 .iotype = UPIO_AU, \
56 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ 56 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
57 UPF_FIXED_TYPE, \ 57 UPF_FIXED_TYPE, \
58 .type = PORT_16550A, \ 58 .type = PORT_16550A, \
59 .pm = alchemy_8250_pm, \ 59 .pm = alchemy_8250_pm, \
@@ -137,7 +137,7 @@ static void alchemy_ehci_power_off(struct platform_device *pdev)
137} 137}
138 138
139static struct usb_ehci_pdata alchemy_ehci_pdata = { 139static struct usb_ehci_pdata alchemy_ehci_pdata = {
140 .no_io_watchdog = 1, 140 .no_io_watchdog = 1,
141 .power_on = alchemy_ehci_power_on, 141 .power_on = alchemy_ehci_power_on,
142 .power_off = alchemy_ehci_power_off, 142 .power_off = alchemy_ehci_power_off,
143 .power_suspend = alchemy_ehci_power_off, 143 .power_suspend = alchemy_ehci_power_off,
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 37ffd997c616..62b4e7bbeab9 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -59,7 +59,7 @@ void __init plat_mem_setup(void)
59 /* Clear to obtain best system bus performance */ 59 /* Clear to obtain best system bus performance */
60 clear_c0_config(1 << 19); /* Clear Config[OD] */ 60 clear_c0_config(1 << 19); /* Clear Config[OD] */
61 61
62 board_setup(); /* board specific setup */ 62 board_setup(); /* board specific setup */
63 63
64 /* IO/MEM resources. */ 64 /* IO/MEM resources. */
65 set_io_port_base(0); 65 set_io_port_base(0);
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index c7bcc7e5c822..706d933e0085 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -102,12 +102,12 @@ LEAF(alchemy_sleep_au1000)
102 cache 0x14, 96(t0) 102 cache 0x14, 96(t0)
103 .set mips0 103 .set mips0
104 104
1051: lui a0, 0xb400 /* mem_xxx */ 1051: lui a0, 0xb400 /* mem_xxx */
106 sw zero, 0x001c(a0) /* Precharge */ 106 sw zero, 0x001c(a0) /* Precharge */
107 sync 107 sync
108 sw zero, 0x0020(a0) /* Auto Refresh */ 108 sw zero, 0x0020(a0) /* Auto Refresh */
109 sync 109 sync
110 sw zero, 0x0030(a0) /* Sleep */ 110 sw zero, 0x0030(a0) /* Sleep */
111 sync 111 sync
112 112
113 DO_SLEEP 113 DO_SLEEP
@@ -128,15 +128,15 @@ LEAF(alchemy_sleep_au1550)
128 cache 0x14, 96(t0) 128 cache 0x14, 96(t0)
129 .set mips0 129 .set mips0
130 130
1311: lui a0, 0xb400 /* mem_xxx */ 1311: lui a0, 0xb400 /* mem_xxx */
132 sw zero, 0x08c0(a0) /* Precharge */ 132 sw zero, 0x08c0(a0) /* Precharge */
133 sync 133 sync
134 sw zero, 0x08d0(a0) /* Self Refresh */ 134 sw zero, 0x08d0(a0) /* Self Refresh */
135 sync 135 sync
136 136
137 /* wait for sdram to enter self-refresh mode */ 137 /* wait for sdram to enter self-refresh mode */
138 lui t0, 0x0100 138 lui t0, 0x0100
1392: lw t1, 0x0850(a0) /* mem_sdstat */ 1392: lw t1, 0x0850(a0) /* mem_sdstat */
140 and t2, t1, t0 140 and t2, t1, t0
141 beq t2, zero, 2b 141 beq t2, zero, 2b
142 nop 142 nop
@@ -144,9 +144,9 @@ LEAF(alchemy_sleep_au1550)
144 /* disable SDRAM clocks */ 144 /* disable SDRAM clocks */
145 lui t0, 0xcfff 145 lui t0, 0xcfff
146 ori t0, t0, 0xffff 146 ori t0, t0, 0xffff
147 lw t1, 0x0840(a0) /* mem_sdconfiga */ 147 lw t1, 0x0840(a0) /* mem_sdconfiga */
148 and t1, t0, t1 /* clear CE[1:0] */ 148 and t1, t0, t1 /* clear CE[1:0] */
149 sw t1, 0x0840(a0) /* mem_sdconfiga */ 149 sw t1, 0x0840(a0) /* mem_sdconfiga */
150 sync 150 sync
151 151
152 DO_SLEEP 152 DO_SLEEP
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index b67930d19325..38afb11ba2c4 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -85,7 +85,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
85 .name = "rtcmatch2", 85 .name = "rtcmatch2",
86 .features = CLOCK_EVT_FEAT_ONESHOT, 86 .features = CLOCK_EVT_FEAT_ONESHOT,
87 .rating = 1500, 87 .rating = 1500,
88 .set_next_event = au1x_rtcmatch2_set_next_event, 88 .set_next_event = au1x_rtcmatch2_set_next_event,
89 .set_mode = au1x_rtcmatch2_set_mode, 89 .set_mode = au1x_rtcmatch2_set_mode,
90 .cpumask = cpu_all_mask, 90 .cpumask = cpu_all_mask,
91}; 91};
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
index 936af8359fb2..fcc695626117 100644
--- a/arch/mips/alchemy/common/usb.c
+++ b/arch/mips/alchemy/common/usb.c
@@ -122,7 +122,7 @@ static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
122 unsigned long r; 122 unsigned long r;
123 123
124 if (enable) { 124 if (enable) {
125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ 125 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
126 wmb(); 126 wmb();
127 127
128 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ 128 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index f2039ef2c293..c98c9ea3372c 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -20,7 +20,7 @@ static struct bcsr_reg {
20 spinlock_t lock; 20 spinlock_t lock;
21} bcsr_regs[BCSR_CNT]; 21} bcsr_regs[BCSR_CNT];
22 22
23static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */ 23static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
24static int bcsr_csc_base; /* linux-irq of first cascaded irq */ 24static int bcsr_csc_base; /* linux-irq of first cascaded irq */
25 25
26void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys) 26void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 8187845650f7..11f3ad20321c 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -276,7 +276,7 @@ static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
276} 276}
277 277
278static struct led_classdev db1100_mmc_led = { 278static struct led_classdev db1100_mmc_led = {
279 .brightness_set = db1100_mmcled_set, 279 .brightness_set = db1100_mmcled_set,
280}; 280};
281 281
282static int db1100_mmc1_card_readonly(void *mmc_host) 282static int db1100_mmc1_card_readonly(void *mmc_host)
@@ -314,7 +314,7 @@ static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
314} 314}
315 315
316static struct led_classdev db1100_mmc1_led = { 316static struct led_classdev db1100_mmc1_led = {
317 .brightness_set = db1100_mmc1led_set, 317 .brightness_set = db1100_mmc1led_set,
318}; 318};
319 319
320static struct au1xmmc_platform_data db1100_mmc_platdata[2] = { 320static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
@@ -357,7 +357,7 @@ static struct resource au1100_mmc0_resources[] = {
357 } 357 }
358}; 358};
359 359
360static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 360static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
361 361
362static struct platform_device db1100_mmc0_dev = { 362static struct platform_device db1100_mmc0_dev = {
363 .name = "au1xxx-mmc", 363 .name = "au1xxx-mmc",
@@ -482,7 +482,7 @@ static struct spi_board_info db1100_spi_info[] __initdata = {
482 .mode = 0, 482 .mode = 0,
483 .irq = AU1100_GPIO21_INT, 483 .irq = AU1100_GPIO21_INT,
484 .platform_data = &db1100_touch_pd, 484 .platform_data = &db1100_touch_pd,
485 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */ 485 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
486 }, 486 },
487}; 487};
488 488
@@ -572,7 +572,7 @@ static int __init db1000_dev_init(void)
572 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW); 572 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
573 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); 573 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
574 /* EPSON S1D13806 0x1b000000 574 /* EPSON S1D13806 0x1b000000
575 * SRAM 1MB/2MB 0x1a000000 575 * SRAM 1MB/2MB 0x1a000000
576 * DS1693 RTC 0x0c000000 576 * DS1693 RTC 0x0c000000
577 */ 577 */
578 } else if (board == BCSR_WHOAMI_PB1100) { 578 } else if (board == BCSR_WHOAMI_PB1100) {
@@ -586,7 +586,7 @@ static int __init db1000_dev_init(void)
586 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW); 586 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
587 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW); 587 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
588 /* EPSON S1D13806 0x1b000000 588 /* EPSON S1D13806 0x1b000000
589 * SRAM 1MB/2MB 0x1a000000 589 * SRAM 1MB/2MB 0x1a000000
590 * DiskOnChip 0x0d000000 590 * DiskOnChip 0x0d000000
591 * DS1693 RTC 0x0c000000 591 * DS1693 RTC 0x0c000000
592 */ 592 */
@@ -605,7 +605,7 @@ static int __init db1000_dev_init(void)
605 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 605 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
606 AU1000_PCMCIA_IO_PHYS_ADDR, 606 AU1000_PCMCIA_IO_PHYS_ADDR,
607 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 607 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
608 c0, d0, /*s0*/0, 0, 0); 608 c0, d0, /*s0*/0, 0, 0);
609 609
610 if (twosocks) { 610 if (twosocks) {
611 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH); 611 irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
@@ -619,7 +619,7 @@ static int __init db1000_dev_init(void)
619 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 619 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
620 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 620 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
621 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 621 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
622 c1, d1, /*s1*/0, 0, 1); 622 c1, d1, /*s1*/0, 0, 1);
623 } 623 }
624 624
625 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); 625 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index 299b7d202bea..a84d98b8f96e 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -90,14 +90,14 @@ int __init db1200_board_setup(void)
90 90
91 whoami = bcsr_read(BCSR_WHOAMI); 91 whoami = bcsr_read(BCSR_WHOAMI);
92 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 92 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
93 " Board-ID %d Daughtercard ID %d\n", get_system_type(), 93 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
94 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 94 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
95 95
96 /* SMBus/SPI on PSC0, Audio on PSC1 */ 96 /* SMBus/SPI on PSC0, Audio on PSC1 */
97 pfc = __raw_readl((void __iomem *)SYS_PINFUNC); 97 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
98 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 98 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
99 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 99 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
100 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 100 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
101 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); 101 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
102 wmb(); 102 wmb();
103 103
@@ -129,7 +129,7 @@ int __init db1200_board_setup(void)
129static struct mtd_partition db1200_spiflash_parts[] = { 129static struct mtd_partition db1200_spiflash_parts[] = {
130 { 130 {
131 .name = "spi_flash", 131 .name = "spi_flash",
132 .offset = 0, 132 .offset = 0,
133 .size = MTDPART_SIZ_FULL, 133 .size = MTDPART_SIZ_FULL,
134 }, 134 },
135}; 135};
@@ -200,12 +200,12 @@ static int au1200_nand_device_ready(struct mtd_info *mtd)
200static struct mtd_partition db1200_nand_parts[] = { 200static struct mtd_partition db1200_nand_parts[] = {
201 { 201 {
202 .name = "NAND FS 0", 202 .name = "NAND FS 0",
203 .offset = 0, 203 .offset = 0,
204 .size = 8 * 1024 * 1024, 204 .size = 8 * 1024 * 1024,
205 }, 205 },
206 { 206 {
207 .name = "NAND FS 1", 207 .name = "NAND FS 1",
208 .offset = MTDPART_OFS_APPEND, 208 .offset = MTDPART_OFS_APPEND,
209 .size = MTDPART_SIZ_FULL 209 .size = MTDPART_SIZ_FULL
210 }, 210 },
211}; 211};
@@ -395,7 +395,7 @@ static void db1200_mmcled_set(struct led_classdev *led,
395} 395}
396 396
397static struct led_classdev db1200_mmc_led = { 397static struct led_classdev db1200_mmc_led = {
398 .brightness_set = db1200_mmcled_set, 398 .brightness_set = db1200_mmcled_set,
399}; 399};
400 400
401/* -- */ 401/* -- */
@@ -463,7 +463,7 @@ static void pb1200_mmc1led_set(struct led_classdev *led,
463} 463}
464 464
465static struct led_classdev pb1200_mmc1_led = { 465static struct led_classdev pb1200_mmc1_led = {
466 .brightness_set = pb1200_mmc1led_set, 466 .brightness_set = pb1200_mmc1led_set,
467}; 467};
468 468
469static void pb1200_mmc1_set_power(void *mmc_host, int state) 469static void pb1200_mmc1_set_power(void *mmc_host, int state)
@@ -526,7 +526,7 @@ static struct resource au1200_mmc0_resources[] = {
526 } 526 }
527}; 527};
528 528
529static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 529static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
530 530
531static struct platform_device db1200_mmc0_dev = { 531static struct platform_device db1200_mmc0_dev = {
532 .name = "au1xxx-mmc", 532 .name = "au1xxx-mmc",
@@ -601,7 +601,7 @@ static int db1200fb_panel_shutdown(void)
601static struct au1200fb_platdata db1200fb_pd = { 601static struct au1200fb_platdata db1200fb_pd = {
602 .panel_index = db1200fb_panel_index, 602 .panel_index = db1200fb_panel_index,
603 .panel_init = db1200fb_panel_init, 603 .panel_init = db1200fb_panel_init,
604 .panel_shutdown = db1200fb_panel_shutdown, 604 .panel_shutdown = db1200fb_panel_shutdown,
605}; 605};
606 606
607static struct resource au1200_lcd_res[] = { 607static struct resource au1200_lcd_res[] = {
@@ -772,11 +772,11 @@ static int __init pb1200_res_fixup(void)
772 } 772 }
773 773
774 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 774 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
775 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 775 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
776 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 776 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
777 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 777 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
778 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 778 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
779 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 779 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
780 return 0; 780 return 0;
781} 781}
782 782
@@ -797,7 +797,7 @@ int __init db1200_dev_setup(void)
797 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 797 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
798 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 798 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
799 799
800 /* insert/eject pairs: one of both is always screaming. To avoid 800 /* insert/eject pairs: one of both is always screaming. To avoid
801 * issues they must not be automatically enabled when initially 801 * issues they must not be automatically enabled when initially
802 * requested. 802 * requested.
803 */ 803 */
@@ -813,7 +813,7 @@ int __init db1200_dev_setup(void)
813 spi_register_board_info(db1200_spi_devs, 813 spi_register_board_info(db1200_spi_devs,
814 ARRAY_SIZE(db1200_i2c_devs)); 814 ARRAY_SIZE(db1200_i2c_devs));
815 815
816 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 816 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
817 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 817 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
818 * or S12 on the PB1200. 818 * or S12 on the PB1200.
819 */ 819 */
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index cdf37cbd3d1f..6167e73eef9c 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -80,7 +80,7 @@ static int db1300_dev_pins[] __initdata = {
80 AU1300_PIN_PSC0D1, 80 AU1300_PIN_PSC0D1,
81 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, 81 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
82 AU1300_PIN_PSC1D1, 82 AU1300_PIN_PSC1D1,
83 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, 83 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
84 AU1300_PIN_PSC2D1, 84 AU1300_PIN_PSC2D1,
85 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, 85 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
86 AU1300_PIN_PSC3D1, 86 AU1300_PIN_PSC3D1,
@@ -143,12 +143,12 @@ static int au1300_nand_device_ready(struct mtd_info *mtd)
143static struct mtd_partition db1300_nand_parts[] = { 143static struct mtd_partition db1300_nand_parts[] = {
144 { 144 {
145 .name = "NAND FS 0", 145 .name = "NAND FS 0",
146 .offset = 0, 146 .offset = 0,
147 .size = 8 * 1024 * 1024, 147 .size = 8 * 1024 * 1024,
148 }, 148 },
149 { 149 {
150 .name = "NAND FS 1", 150 .name = "NAND FS 1",
151 .offset = MTDPART_OFS_APPEND, 151 .offset = MTDPART_OFS_APPEND,
152 .size = MTDPART_SIZ_FULL 152 .size = MTDPART_SIZ_FULL
153 }, 153 },
154}; 154};
@@ -487,7 +487,7 @@ static void db1300_mmcled_set(struct led_classdev *led,
487} 487}
488 488
489static struct led_classdev db1300_mmc_led = { 489static struct led_classdev db1300_mmc_led = {
490 .brightness_set = db1300_mmcled_set, 490 .brightness_set = db1300_mmcled_set,
491}; 491};
492 492
493struct au1xmmc_platform_data db1300_sd1_platdata = { 493struct au1xmmc_platform_data db1300_sd1_platdata = {
@@ -646,7 +646,7 @@ static int db1300fb_panel_shutdown(void)
646static struct au1200fb_platdata db1300fb_pd = { 646static struct au1200fb_platdata db1300fb_pd = {
647 .panel_index = db1300fb_panel_index, 647 .panel_index = db1300fb_panel_index,
648 .panel_init = db1300fb_panel_init, 648 .panel_init = db1300fb_panel_init,
649 .panel_shutdown = db1300fb_panel_shutdown, 649 .panel_shutdown = db1300fb_panel_shutdown,
650}; 650};
651 651
652static struct resource au1300_lcd_res[] = { 652static struct resource au1300_lcd_res[] = {
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
index 5a9ae6095428..016cddacd7ea 100644
--- a/arch/mips/alchemy/devboards/db1550.c
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -67,7 +67,7 @@ int __init db1550_board_setup(void)
67 bcsr_init(PB1550_BCSR_PHYS_ADDR, 67 bcsr_init(PB1550_BCSR_PHYS_ADDR,
68 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); 68 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
69 69
70 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \ 70 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
71 "Daughtercard ID %d\n", get_system_type(), 71 "Daughtercard ID %d\n", get_system_type(),
72 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 72 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
73 73
@@ -80,7 +80,7 @@ int __init db1550_board_setup(void)
80static struct mtd_partition db1550_spiflash_parts[] = { 80static struct mtd_partition db1550_spiflash_parts[] = {
81 { 81 {
82 .name = "spi_flash", 82 .name = "spi_flash",
83 .offset = 0, 83 .offset = 0,
84 .size = MTDPART_SIZ_FULL, 84 .size = MTDPART_SIZ_FULL,
85 }, 85 },
86}; 86};
@@ -151,12 +151,12 @@ static int au1550_nand_device_ready(struct mtd_info *mtd)
151static struct mtd_partition db1550_nand_parts[] = { 151static struct mtd_partition db1550_nand_parts[] = {
152 { 152 {
153 .name = "NAND FS 0", 153 .name = "NAND FS 0",
154 .offset = 0, 154 .offset = 0,
155 .size = 8 * 1024 * 1024, 155 .size = 8 * 1024 * 1024,
156 }, 156 },
157 { 157 {
158 .name = "NAND FS 1", 158 .name = "NAND FS 1",
159 .offset = MTDPART_OFS_APPEND, 159 .offset = MTDPART_OFS_APPEND,
160 .size = MTDPART_SIZ_FULL 160 .size = MTDPART_SIZ_FULL
161 }, 161 },
162}; 162};
@@ -495,10 +495,10 @@ static void __init db1550_devices(void)
495{ 495{
496 alchemy_gpio_direction_output(203, 0); /* red led on */ 496 alchemy_gpio_direction_output(203, 0); /* red led on */
497 497
498 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ 498 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
499 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ 499 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
500 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ 500 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
501 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ 501 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
502 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ 502 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
503 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ 503 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
504 504
@@ -539,7 +539,7 @@ static void __init pb1550_devices(void)
539 539
540 /* Pb1550, like all others, also has statuschange irqs; however they're 540 /* Pb1550, like all others, also has statuschange irqs; however they're
541 * wired up on one of the Au1550's shared GPIO201_205 line, which also 541 * wired up on one of the Au1550's shared GPIO201_205 line, which also
542 * services the PCMCIA card interrupts. So we ignore statuschange and 542 * services the PCMCIA card interrupts. So we ignore statuschange and
543 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia 543 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
544 * drivers are used to shared irqs and b) statuschange isn't really use- 544 * drivers are used to shared irqs and b) statuschange isn't really use-
545 * ful anyway. 545 * ful anyway.
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index acaf91b5e461..b86bff31d1d3 100644
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -194,7 +194,7 @@ static ssize_t db1x_pmattr_store(struct kobject *kobj,
194} 194}
195 195
196#define ATTR(x) \ 196#define ATTR(x) \
197 static struct kobj_attribute x##_attribute = \ 197 static struct kobj_attribute x##_attribute = \
198 __ATTR(x, 0664, db1x_pmattr_show, \ 198 __ATTR(x, 0664, db1x_pmattr_show, \
199 db1x_pmattr_store); 199 db1x_pmattr_store);
200 200
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 19:59:57 -0500